Reducing read transactions to peripheral devices

Patent metadata

Field	Value
Publication number	US-10521377-B1
Application number	US-201816197289-A
Country	US
Kind code	B1
Filing date	Nov 20, 2018
Priority date	Mar 31, 2016
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A first write transaction is received by a device that includes a transaction identifier and a memory location identifier. The memory location identifies a register or a memory location of a device. A value from the register or memory location is read. A second write transaction is sent to a block of host memory. The second write transaction includes the value and the transaction identifier.

First claim

What is claimed is:

1. A computing system comprising:
a host memory;
a host processor configured to communicate with the host memory; and
a driver running on an operating system of the host processor, wherein the driver is configured to:
transmit a first write transaction to a first register or a first memory location of a peripheral device, the first write transaction including a transaction identifier and a memory location identifier; and
receive from the peripheral device a second write transaction to a block of the host memory, wherein the memory location identifier identifies a second register or a second memory location of the peripheral device, and wherein the second write transaction includes the transaction identifier, the memory location identifier, and a value contained in the second register or second memory location.

2. The computing system of claim 1 , wherein the memory location identifier identifies the second register or the second memory location by an offset value.

3. The computing system of claim 1 , wherein the driver is further configured to:
transmit a read response address to the peripheral device before transmitting the first write transaction, the read response address indicating the block of the host memory for receiving the value contained in the second register or second memory location.

4. The computing system of claim 1 , wherein the host processor is configured to:
read the transaction identifier from the block of the host memory;
read the value from the block of the host memory; and
execute a function that utilizes the value.

5. The computing system of claim 4 , wherein the host processor is further configured to:
verify that the memory location identifier sent in the first write transaction matches the memory location identifier received in the second write transaction.

6. The computing system of claim 1 , wherein the second write transaction is a direct memory access (DMA) write transaction.

7. The computing system of claim 1 , wherein the driver is further configured to:
determine whether a response is received from the peripheral device within a predetermined period of time after transmitting the first write transaction; and
in response to determining that the response is not received from the peripheral device, cancel the first write transaction.

8. The computing system of claim 1 , wherein the driver is further configured to:
determine whether a response is received from the peripheral device within a predetermined period of time after transmitting the first write transaction; and
in response to determining that the response is not received from the peripheral device, transmit a third write transaction having a retransmission transaction identifier different than the transaction identifier of the first write transaction.

9. The computing system of claim 1 , wherein transmitting the first write transaction and receiving the second write transaction is performed synchronously.

10. The computing system of claim 1 , wherein transmitting the first write transaction and receiving the second write transaction is performed asynchronously.

11. A method for reducing read transactions to a peripheral device, the method comprising:
transmitting, by a driver running on an operating system of a host processor of a computing system, a first write transaction to a first register or a first memory location of a peripheral device, the first write transaction including a transaction identifier and a memory location identifier; and
receiving, by the driver, a second write transaction to a block of host memory, wherein the second write transaction is received from the peripheral device, wherein the memory location identifier identifies a second register or a second memory location of the peripheral device, and wherein the second write transaction includes the transaction identifier, the memory location identifier, and a value contained in the second register or second memory location.

12. The method of claim 11 , wherein the memory location identifier identifies the second register or the second memory location by an offset value.

13. The method of claim 11 , further comprising:
transmitting, by the driver, a read response address indicating a block of a host memory for receiving the value, wherein the driver transmits the read response address before transmitting the first write transaction.

14. The method of claim 11 , further comprising:
reading, by the host processor, the transaction identifier from the block of host memory;
reading, by the host processor, the value from the block of host memory; and
executing, by the host processor, a function that utilizes the value.

15. The method of claim 14 , further comprising:
verifying, by the host processor, that the memory location identifier sent in the first write transaction matches the memory location identifier received in the second write transaction.

16. The method of claim 11 , wherein the second write transaction is a direct memory access (DMA) write transaction.

17. The method of claim 11 , further comprising:
determining, by the driver, whether a response is received from the peripheral device within a predetermined period of time after transmitting the first write transaction; and
in response to determining that the response is not received from the peripheral device, cancel the first write transaction.

18. The method of claim 11 , further comprising:
determining, by the driver, whether a response is received from the peripheral device within a predetermined period of time after transmitting the first write transaction; and
in response to determining that the response is not received from the peripheral device, transmit a third write transaction having a retransmission transaction identifier different than the transaction identifier of the first write transaction.

19. The method of claim 11 , wherein the transmitting the first write transaction and the receiving the second write transaction is performed synchronously.

20. The method of claim 11 , wherein the transmitting the first write transaction and the receiving the second write transaction are performed asynchronously.

Assignees

• Amazon Tech Inc

Inventors

• Machulsky Georgy
• Bshara Nafea
• Belgazal Netanel Israel
• Bshara Said
• Schmeilin Evgeny

Classifications

• G06F2213/0024

  Peripheral component interconnect [PCI] · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title