Coalescing periodic timer expiration in guest operating systems in a virtualized environment

US10521265B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10521265-B2
Application numberUS-23435308-A
CountryUS
Kind codeB2
Filing dateSep 19, 2008
Priority dateSep 19, 2008
Publication dateDec 31, 2019
Grant dateDec 31, 2019

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  1. Title

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  5. First independent claim

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Abstract

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Techniques are disclosed for coalescing timer ticks generated by timers used to service guest operating systems executing in virtual machines. By coalescing timer ticks a logical processor can enter a low power mode thereby reducing power consumed by the system.

First claim

Opening claim text (preview).

What is claimed: 1. A method for coalescing interrupts, comprising: receiving, by a first virtual timer of a first virtual machine, a request for periodic interrupts at a first interval from a first guest operating system executing on the first virtual machine; receiving, by a second virtual timer of a second virtual machine, a request for periodic interrupts at a second interval from a second guest operating system executing on the second virtual machine; determining, based on the first interval, a first system time range for the first virtual machine, the first system time range comprising a minimum system time and a maximum system time for generating a periodic interrupt for the first virtual machine within a tolerance of the first guest operating system; determining, based on the second interval, a second system time range for the second virtual machine, the second system time range comprising a minimum system time and a maximum system time for generating a periodic interrupt for the second virtual machine within a tolerance of the second guest operating system determining an interrupt time range, the interrupt time range being the intersection between the first system time range and the second system time range, and setting a hardware timer to expire at first system time within the interrupt time range; and sending, in response to the hardware timer expiring at the first system time, a virtual timer interrupt to each of the first virtual machine and the second virtual machine. 2. The method of claim 1 , further comprising: receiving an asynchronous interrupt prior to the first system time; determining whether a current system time is within the interrupt time range in response to receiving the asynchronous interrupt; and sending a virtual timer interrupt to each of the first virtual machine and the second virtual machine in response to determining the current system time is within the interrupt time range. 3. The method of claim 2 , wherein the method further comprises: clearing the set timer in response to sending the virtual timer interrupts. 4. The method of claim 2 , wherein the asynchronous interrupt was generated by a hardware device. 5. The method of claim 1 , wherein the first interval is different form the second interval. 6. The method of claim 5 , wherein determining the first system time range further comprises: determining a second system time that is a multiple of the first interval, wherein the second system time is within the first system time range. 7. The method of claim 6 , wherein determining the second system time further comprises: determining a third system time that is a multiple of the second interval, wherein the third system time that is within the second system time range. 8. A system for coalescing interrupts comprising: circuitry configured to receive a signal from a first guest operating system executing on a first virtual machine, the signal programming a virtual timer of the first virtual machine to generate periodic interrupts at a first interval; circuitry configured to receive a second signal from a second guest operating system executing on a second virtual machine, the second signal programming a virtual timer of the second virtual machine to generate periodic interrupts at a second interval; circuitry configured to determine based on the first interval, a first system time range for the first virtual machine, the first system time range comprising a minimum system time and a maximum system time for generating a periodic interrupt for the first virtual machine within a tolerance of the first guest operating system; circuitry configured to determine, based on the second interval, a second system time range for the second virtual machine, the second system time range comprising a minimum system time and a maximum system time for generating a periodic interrupt for the second virtual machine within a tolerance of the second guest operating system circuitry configured to determine an interrupt time range, the interrupt time range being the intersection between the first system time range and the second system time range, and set a hardware timer to expire at a first system time within the interrupt time range; and circuitry configured to send, in response to the hardware timer expiring at the first system time, a virtual timer interrupt to each of the first virtual machine and the second virtual machine. 9. The system of claim 8 , further comprising: circuitry configured to receive an asynchronous interrupt prior to the first system time; circuitry configured to determine whether a current system time is within the interrupt time range in response to receiving the asynchronous interrupt; and circuitry configured to send a virtual timer interrupt to each of the first virtual machine and the second virtual machine in response to determining the current system time is within the interrupt time range. 10. The system of claim 9 , further comprising: circuitry configured to clear the set timer in response to sending the virtual timer interrupts. 11. The system of claim 9 , wherein the asynchronous interrupt was generated by a hardware device. 12. The system of claim 9 , wherein the asynchronous interrupt comprises a hypercall. 13. The system of claim 9 , wherein the asynchronous interrupt comprises a hypervisor intercept. 14. A computer readable hardware storage device including computer executable instructions for coalescing interrupts, the computer readable hardware storage device comprising: instructions for receiving, by a first virtual timer of a first virtual machine, a request for a periodic interrupts at a first interval from a first guest operating system executing on the first virtual machine; instructions for receiving, by a second virtual timer of a second virtual machine, a request for a periodic interrupts at a second interval from a second guest operating system executing on the second virtual machine; instructions for determining, based on the first interval, a first system time range for the first virtual machine, the first system time range comprising a minimum system time and a maximum system time for generating a periodic interrupt for the first virtual machine within a tolerance of the first guest operating system; instructions for determining based on the second interval a second system time range for the second virtual machine, the second system time range comprising a minimum system time and a maximum system time for generating a periodic interrupt for the second virtual machine within a tolerance of the second guest operating system; and instructions for determining an interrupt time range, the interrupt time range being the intersection between the first system time range and the second system time range, and setting a hardware timer to expire at a first system time within the interrupt time range; and sending, in response to the hardware timer expiring at the first system time, a virtual timer interrupt to each of the first virtual machine and the second virtual machine. 15. The computer readable storage device of claim 14 , further comprising: instructions for receiving an asynchronous interrupt prior to the first system time; instructions for determining whether a current system time is within the interrupt time range in response to receiving the asynchronous interrupt; and instructions for sending a virtual timer interrupt to each of the first virtual machine and the second virtual machine in response to determining the current system time is within the interrupt time range. 16. The computer read

Assignees

Inventors

Classifications

  • Hypervisors; Virtual machine monitors · CPC title

  • G06F9/4812Primary

    by interrupt, e.g. masked · CPC title

  • Cross-Sectional Technologies · mapped topic

  • Cross-Sectional Technologies · mapped topic

  • Cross-Sectional Technologies · mapped topic

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Frequently asked questions

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What does patent US10521265B2 cover?
Techniques are disclosed for coalescing timer ticks generated by timers used to service guest operating systems executing in virtual machines. By coalescing timer ticks a logical processor can enter a low power mode thereby reducing power consumed by the system.
Who is the assignee on this patent?
Wang Haiyong, Baker Brandon S, Ganguly Shuvabrata, and 2 more
What technology area does this patent fall under?
Primary CPC classification G06F9/4812. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 31 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).