Microprocessor accelerated code optimizer

Patent metadata

Field	Value
Publication number	US-10521239-B2
Application number	US-201615283836-A
Country	US
Kind code	B2
Filing date	Oct 3, 2016
Priority date	Nov 22, 2011
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A method for accelerating code optimization a microprocessor. The method includes fetching an incoming microinstruction sequence using an instruction fetch component and transferring the fetched macroinstructions to a decoding component for decoding into microinstructions. Optimization processing is performed by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups. The optimized microinstruction sequence is output to a microprocessor pipeline for execution. A copy of the optimized microinstruction sequence is stored into a sequence cache for subsequent use upon a subsequent hit optimized microinstruction sequence.

First claim

What is claimed is:

1. In a microprocessor, a method for accelerating code optimization, the method comprising:
accessing an input microinstruction sequence by using an optimizer instantiated in memory;
executing a plurality of single instruction multiple data (SIMD) compare instructions to compare registers used by instructions in the input microinstruction sequence in parallel;
using a result of executing the plurality of SIMD compare instructions to populate a dependency matrix with dependency information extracted from the input microinstruction sequence;
scanning a plurality of rows of the dependency matrix to perform instruction processing by reordering the input microinstruction sequence into an enhanced microinstruction sequence comprising a plurality of dependent code groups;
outputting the enhanced microinstruction sequence to a microprocessor pipeline for execution; and
storing a copy of the enhanced microinstruction sequence into a sequence cache for subsequent use upon a subsequent hit to the enhanced microinstruction sequence.

2. The method of claim 1 , wherein the instruction processing further comprises scanning the plurality of rows of the dependency matrix to identify matching instructions.

3. The method of claim 2 , wherein the instruction processing further comprises analyzing the matching instructions to determine whether the matching instructions comprise a blocking dependency, and wherein renaming is performed to remove the blocking dependency.

4. The method of claim 3 , wherein instructions corresponding to first matches of each row of the dependency matrix are moved into a corresponding dependency group.

5. The method of claim 1 , wherein copies of enhanced microinstruction sequences are stored in a memory hierarchy of the microprocessor.

6. The method of claim 5 , wherein the memory hierarchy comprises an L1 cache and an L2 cache.

7. The method of claim 1 , wherein the executing the plurality of SIMD compare instructions comprises:
performing a pairing match to determine the dependency information.

8. The method of claim 1 , wherein the executing the plurality of SIMD compare instructions comprises:
performing a blocking match to determine the dependency information.

9. The method of claim 8 , wherein the blocking match is resolved by register renaming.

10. A microprocessor comprising:
an instruction fetch component for fetching an incoming macroinstruction sequence;
a decoding component coupled to the instruction fetch component operable to receive and decode the incoming macroinstruction sequence into a microinstruction sequence;
an optimizer operable to be instantiated in memory for accessing the microinstruction sequence and executing a plurality of single instruction multiple data (SIMD) compare instructions to compare registers used by instructions in the microinstruction sequence in parallel;
a dependency matrix operable to be populated with dependency information extracted from the microinstruction sequence using a result of executing the plurality of SIMD compare instructions, wherein a plurality of rows of the dependency matrix are scanned to perform instruction processing using the optimizer by reordering the microinstruction sequence into an updated microinstruction sequence comprising a plurality of dependent code groups; and
a sequence cache operable to receive and store a copy of the updated microinstruction sequence for subsequent use upon a subsequent hit on the updated microinstruction sequence.

11. The microprocessor of claim 10 , wherein the instruction processing further comprises scanning the plurality of rows of the dependency matrix to identify matching instructions.

12. The microprocessor of claim 11 , wherein the instruction processing further includes analyzing the matching instructions to determine whether the matching instructions comprise a blocking dependency, and wherein renaming is performed to remove the blocking dependency.

13. The microprocessor of claim 12 , wherein instructions corresponding to first matches of each row of the dependency matrix are moved into a corresponding dependency group.

14. In a microprocessor, a method for accelerating code optimization, the method comprising:
accessing an input microinstruction sequence by using an optimizer instantiated in memory, wherein the optimizer is a software-based optimizer;
executing a plurality of single instruction multiple data (SIMD) compare instructions to compare registers used by instructions in the input microinstruction sequence in parallel;
using a result of executing the plurality of SIMD compare instructions to populate a dependency matrix with dependency information extracted from the input microinstruction sequence;
scanning a plurality of rows of the dependency matrix to perform instruction processing by reordering the input microinstruction sequence into an enhanced microinstruction sequence comprising a plurality of dependent code groups;
outputting the enhanced microinstruction sequence to a microprocessor pipeline for execution; and
storing a copy of the enhanced microinstruction sequence in a memory hierarchy.

15. The method of claim 14 , wherein the instruction processing further comprises scanning the plurality of rows of the dependency matrix to identify matching instructions.

16. The method of claim 15 , wherein the instruction processing further comprises analyzing the matching instructions to determine whether the matching instructions comprise a blocking dependency, and wherein renaming is performed to remove the blocking dependency.

17. The method of claim 16 , wherein instructions corresponding to first matches of each row of the dependency matrix are moved into a corresponding dependency group.

18. The method of claim 14 , wherein the executing the plurality of SIMD compare instructions comprises:
performing a pairing match to determine the dependency information.

19. The method of claim 14 , wherein the executing the plurality of SIMD compare instructions comprises:
performing a blocking match to determine the dependency information.

20. The method of claim 19 , wherein the blocking match can be resolved by register renaming.

Assignees

• Intel Corp

Inventors

• Abdallah Mohammad

Classifications

• G06F9/30174

  for non-native instruction set, e.g. Javabyte, legacy code · CPC title

• G06F9/3853

  of compound instructions · CPC title

• G06F9/3838

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/3887 Primary

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title