Data processing apparatus and method for processing a SIMD instruction specifying a control value having a first portion identifying a selected data size and a second portion identifying at least one control parameter having a number of bits that varies in dependence on a number of bits comprised by the first portion

Patent metadata

Field	Value
Publication number	US-10521232-B2
Application number	US-201715431955-A
Country	US
Kind code	B2
Filing date	Feb 14, 2017
Priority date	Nov 23, 2010
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element.

First claim

We claim:

1. A data processing apparatus comprising:
processing circuitry configured to perform processing operations; and
an instruction decoder responsive to program instructions to generate control signals for controlling said processing circuitry to perform said processing operations, wherein:
said program instructions include at least one single-instruction-multiple-data (SIMD) instruction identifying a source data value comprising at least one source data element, and specifying a control value having a first portion for indicating a selected data element size of each source data element of said source data value, said selected data element size selected from a plurality of data element sizes, said control value also having a second portion for indicating a plurality of control parameters having a number of bits that varies in dependence on said selected data element size, said first portion and said second portion each having a variable number of bits;
the at least one SIMD instruction has an encoding in which at least one bit of the control value used to represent part of said first portion when the selected data element size is a first data size is also used to represent part of said second portion when the selected data element size is a second data size;
said instruction decoder is responsive to said at least one SIMD instruction to generate control signals for controlling said processing circuitry to perform a corresponding processing operation on each of said at least one source data element of said source data value, in dependence on said selected data element size and said plurality of control parameters;
when processing said at least one SIMD instruction, at least one of said instruction decoder and said processing circuitry is configured to identify the number of bits comprised by said first portion of said control value and, in dependence on said number of bits comprised by said first portion, to identify (a) said selected data element size, and (b) which bits of said control value form said second portion for indicating said plurality of control parameters;
when processing said at least one SIMD instruction, said at least one of said instruction decoder and said processing circuitry is configured to identify, in dependence on said number of bits comprised by said first portion, which bits of said second portion indicate each of said plurality of control parameters;
said plurality of control parameters comprise at least a first control parameter having a number of bits that increases as said selected data element size increases, and a second control parameter having a number of bits that decreases as said selected data element size increases; and
said second portion includes a sub-portion for indicating said first control parameter and said second control parameter, said at least one of said instruction decoder and said processing circuitry identifying, in dependence on said number of bits comprised by said first portion, which bits of said sub-portion indicate said first control parameter and which bits of said sub-portion indicate said second control parameter.

2. The data processing apparatus according to claim 1 , wherein the number of bits of said first portion increases in dependence on said selected data element size as the number of bits of said second portion decreases in dependence on said selected data element size.

3. The data processing apparatus according to claim 1 , wherein for at least a subset of said plurality of data element sizes, said first portion comprises at least a first bit having a first state and X remaining bits having a second state, where X is a variable integer greater than, or equal to, 0; and
said at least one of said instruction decoder and said processing circuitry is configured to identify the number of bits comprised by said first portion of said control value in dependence on a bit position of said first bit within a predetermined portion of said control value.

4. The data processing apparatus according to claim 3 , wherein said first portion comprises at least one additional bit for providing further information for identifying said selected data element size.

5. A virtual machine provided by a computer program stored on a non-transitory computer-readable storage medium, which, when executed by a computer, provides an instruction execution environment according to the data processing apparatus as claimed in claim 1 .

6. A data processing apparatus comprising:
processing circuitry configured to perform processing operations; and
an instruction decoder responsive to program instructions to generate control signals for controlling said processing circuitry to perform said processing operations, wherein:
said program instructions include at least one single-instruction-multiple-data (SIMD) instruction identifying a source data value comprising at least one source data element, and specifying a control value having a first portion for indicating a selected data element size of each source data element of said source data value, said selected data element size selected from a plurality of data element sizes, said control value also having a second portion for indicating at least one control parameter having a number of bits that varies in dependence on said selected data element size, said first portion and said second portion each having a variable number of bits;
the at least one SIMD instruction has an encoding in which at least one bit of the control value used to represent part of said first portion when the selected data element size is a first data size is also used to represent part of said second portion when the selected data element size is a second data size;
said instruction decoder is responsive to said at least one SIMD instruction to generate control signals for controlling said processing circuitry to perform a corresponding processing operation on each of said at least one source data element of said source data value, in dependence on said selected data element size and said at least one control parameter;
when processing said at least one SIMD instruction, at least one of said instruction decoder and said processing circuitry is configured to identify the number of bits comprised by said first portion of said control value and, in dependence on said number of bits comprised by said first portion, to identify (a) said selected data element size, and (b) which bits of said control value form said second portion for indicating said at least one control parameter; and
said at least one SIMD instruction includes a bitfield manipulation instruction and for said bitfield manipulation instruction:
said corresponding processing operation comprises generating a result data value comprising at least one result data element, each result data element corresponding to a corresponding source data element of said source data value;
each result data element comprises a result bitfield having bit values corresponding to bit values of a source bitfield of consecutive bits within said corresponding source data element; and
said at least one control parameter indicates the number of bits comprised by said source bitfield and said result bitfield, a position of said source bitfield within said corresponding source data element, and a position of said result bitfield within said at least one result data element.

7. The data processing apparatus according to claim 6 , wherein for said bitfield manipulation instruction, if said source data value comprises a plurality of source data elements and said result data value comprises a plurality of result data elements, then said at least one control parameter also includes a data element ordering parameter for indicating an order with which said plurality of result data elements

Assignees

• Advanced Risc Mach Ltd

Inventors

• Seal David James
• Grisenthwaite Richard Roy
• Stephens Nigel John

Classifications

• G06F9/30112

  comprising data of variable length · CPC title

• G06F9/3016

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F7/764

  Masking · CPC title

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/30167 Primary

  of immediate specifier, e.g. constants · CPC title