Computational memory cell and processing array device using memory cells

Patent metadata

Field	Value
Publication number	US-10521229-B2
Application number	US-201715709379-A
Country	US
Kind code	B2
Filing date	Sep 19, 2017
Priority date	Dec 6, 2016
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.

First claim

The invention claimed is:

1. A memory computation cell, comprising:
a memory cell having a storage cell, a read port for reading data from the storage cell and a write port for writing data to the storage cell;
an isolation circuit that isolates a data signal representing a piece of data stored in the storage cell from a read bit line, wherein the isolation circuit further comprises a first transistor whose gate is coupled to the read word line and a second transistor whose gate is coupled to the data signal and the isolation circuit first and second transistors are both PMOS transistors;
the read port having a read word line that is coupled to the isolation circuit and activates the isolation circuit and the read bit line that is coupled to the isolation circuit;
the write port having a write word line, a write bit line and complementary write bit line coupled to the memory cell;
wherein the memory cell is capable of being coupled to another memory cell on the read bit line to perform a computational operation; and
wherein the read bit line is capable of being used to provide read access to the storage cell data.

2. A memory computation cell, comprising:
a memory cell having a storage cell, a read port for reading data from the storage cell and a write port for writing data to the storage cell, the storage cell further comprises a first inverter having an input and an output and a second inverter having an input coupled to the output of the first inverter and an output coupled to the input of the first inverter, a first access transistor coupled to the input of the first inverter and the output of the second inverter and a gate of the first access transistor coupled to a write bit line and a second access transistor coupled to the output of the first inverter and the input of the second inverter and a gate of the second access transistor coupled to a complementary write bit line;
an isolation circuit that isolates a data signal representing a piece of data stored in the storage cell from a read bit line;
the read port having a read word line that is coupled to the isolation circuit and activates the isolation circuit and the read bit line that is coupled to the isolation circuit;
the write port having a write word line, a write bit line and complementary write bit line coupled to the memory cell, wherein the write port further comprises a write word line coupled to a gate of a write port transistor, a drain of the write port transistor coupled to a source of the first access transistor and a source of the second access transistor;
wherein the memory cell is capable of being coupled to another memory cell on the read bit line to perform a computational operation; and
wherein the read bit line is capable of being used to provide read access to the storage cell data.

3. The cell of claim 2 , wherein the isolation circuit further comprises a first transistor whose gate is coupled to the read word line and a second transistor whose gate is coupled to the data signal.

4. The cell of claim 3 , wherein the isolation circuit first and second transistors are both NMOS transistors.

5. The cell of claim 2 , wherein the data signal is one of a value of the piece of data and a complementary data signal.

6. A memory computation cell, comprising:
a memory cell having a storage cell, a read port for reading data from the storage cell and a write port for writing data to the storage cell, wherein the storage cell further comprises a first inverter having an input and an output and a second inverter having an input coupled to the output of the first inverter and an output coupled to the input of the first inverter, a first access transistor coupled to the input of the first inverter and the output of the second inverter and a gate coupled to a write bit line and a second access transistor coupled to the output of the first inverter and the input of the second inverter and a gate coupled to a complementary write bit line and wherein the write port further comprises a write word line coupled to a gate of a first write port transistor and a gate of a second write port transistor, a drain of the first write port transistor coupled to a source of the first access transistor and a drain of the second write port transistor coupled to a source of the second access transistor;
an isolation circuit that isolates a data signal representing a piece of data stored in the storage cell from a read bit line;
the read port having a read word line that is coupled to the isolation circuit and activates the isolation circuit and the read bit line that is coupled to the isolation circuit;
the write port having a write word line, a write bit line and complementary write bit line coupled to the memory cell;
wherein the memory cell is capable of being coupled to another memory cell on the read bit line to perform a computational operation; and
wherein the read bit line is capable of being used to provide read access to the storage cell data.

7. A memory computation cell, comprising:
a memory cell having a storage cell, a read port for reading data from the storage cell and a write port for writing data to the storage cell, wherein the storage cell further comprises a first inverter having an input and an output and a second inverter having an input coupled to the output of the first inverter and an output coupled to the input of the first inverter, a first access transistor coupled to the input of the first inverter and the output of the second inverter and a gate of the first access transistor being coupled to a write word line and a second access transistor coupled to the output of the first inverter and the input of the second inverter and a gate of the second access transistor being coupled to the write word line;
an isolation circuit that isolates a data signal representing a piece of data stored in the storage cell from a read bit line;
the read port having a read word line that is coupled to the isolation circuit and activates the isolation circuit and the read bit line that is coupled to the isolation circuit;
the write port having a write word line, a write bit line and complementary write bit line coupled to the memory cell, wherein the write port further comprises a first write port transistor whose gate is coupled to a complementary write bit line and whose drain is coupled to a source of the first access transistor and a second write port transistor whose gate is coupled to a write bit line and whose drain is coupled to a source of the second access transistor;
wherein the memory cell is capable of being coupled to another memory cell on the read bit line to perform a computational operation; and
wherein the read bit line is capable of being used to provide read access to the storage cell data.

8. The cell of claim 2 , wherein the cell is capable of a selective write operation.

9. The cell of claim 2 , wherein the cell is capable of at least one of a boolean AND operation, a boolean NOR operation, a boolean NAND operation and a boolean OR operation.

10. The cell of claim 2 that is a static random access memory cell.

11. The cell of claim 10 , wherein the static random access memory cell is one of a two port static random access memory cell, a three port static random access memory cell and a four port static random access memory cell.

Assignees

• Gsi Technology Inc

Inventors

• Shu Lee-Lean
• Chang Chao-Hung
• Akerib Avidan

Classifications

• G06F9/30043 Primary

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/30029

  Logical and Boolean instructions, e.g. XOR, NOT · CPC title

• G11C11/418

  Address circuits · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G11C11/412

  using field-effect transistors only · CPC title