Storage device array integration of dual-port NVMe device with DRAM cache and hostside portion of software stack system and method

Patent metadata

Field	Value
Publication number	US-10521137-B1
Application number	US-201715798775-A
Country	US
Kind code	B1
Filing date	Oct 31, 2017
Priority date	Oct 31, 2017
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A method, computer program product, and computer system for receiving, by a computing device, a write I/O to a storage device array coupled to a cache, wherein the write I/O may be received from a host. A cache miss in the cache may be determined for the write I/O. One or more free pages may be allocated at an address in the cache to store data for the write I/O. The address in the cache to store the data may be sent to a hostside portion of a software stack in the storage device array. The data may be written directly from the hostside portion to the cache at the address.

First claim

What is claimed is:

1. A computer-implemented method comprising:
receiving, by a computing device, a write I/O to a storage device array coupled to a cache, wherein the write I/O is received from a host;
determining a cache miss in the cache for the write I/O;
allocating one or more free pages at an address in the cache to store data for the write I/O;
sending, to a hostside portion of a software stack in the storage device array, the address in the cache to store the data;
writing the data directly from the hostside portion to the cache at the address;
writing the data to at least two different NVMe devices on a first storage processor; and
syncing cache page metadata associated with the one or more free pages from the first storage processor to a second storage processor.

2. The computer-implemented method of claim 1 wherein the software stack includes a miniport adapter in the storage device array.

3. The computer-implemented method of claim 1 further comprising combining the at least two NVMe devices into a RAID group.

4. The computer-implemented method of claim 3 further comprising generating at least two logical unit numbers for the RAID group.

5. The computer-implemented method of claim 4 wherein a first logical unit number of the least two logical unit numbers includes cache page metadata associated with the one or more free pages and wherein a second logical unit number of the least two logical unit numbers includes the data for the write I/O.

6. A computer program product residing on a non-transitory computer readable storage medium having a plurality of instructions stored thereon which, when executed across one or more processors, causes at least a portion of the one or more processors to perform operations comprising:
receiving a write I/O to a storage device array coupled to a cache, wherein the write I/O is received from a host;
determining a cache miss in the cache for the write I/O;
allocating one or more free pages at an address in the cache to store data for the write I/O;
sending, to a hostside portion of a software stack in the storage device array, the address in the cache to store the data;
writing the data directly from the hostside portion to the cache at the address;
writing the data to at least two different NVMe devices on a first storage processor; and
syncing cache page metadata associated with the one or more free pages from the first storage processor to a second storage processor.

7. The computer program product of claim 6 wherein the software stack includes a miniport adapter in the storage device array.

8. The computer program product of claim 6 wherein the operations further comprise combining the at least two NVMe devices into a RAID group.

9. The computer program product of claim 8 wherein the operations further comprise generating at least two logical unit numbers for the RAID group.

10. The computer program product of claim 9 wherein a first logical unit number of the least two logical unit numbers includes cache page metadata associated with the one or more free pages and wherein a second logical unit number of the least two logical unit numbers includes the data for the write I/O.

11. A computing system including one or more processors and one or more memories configured to perform operations comprising:
receiving a write I/O to a storage device array coupled to a cache, wherein the write I/O is received from a host;
determining a cache miss in the cache for the write I/O;
allocating one or more free pages at an address in the cache to store data for the write I/O;
sending, to a hostside portion of a software stack in the storage device array, the address in the cache to store the data;
writing the data directly from the hostside portion to the cache at the address;
writing the data to at least two different NVMe devices on a first storage processor; and
syncing cache page metadata associated with the one or more free pages from the first storage processor to a second storage processor.

12. The computing system of claim 11 wherein the software stack includes a miniport adapter in the storage device array.

13. The computing system of claim 11 wherein the operations further comprise combining the at least two NVMe devices into a RAID group.

14. The computing system of claim 13 wherein the operations further comprise generating at least two logical unit numbers for the RAID group, wherein a first logical unit number of the least two logical unit numbers includes the cache page metadata associated with the one or more free pages and wherein a second logical unit number of the least two logical unit numbers includes the data for the write I/O.

Assignees

• Emc Ip Holding Co Llc

Inventors

• Xu Xinlei
• Gao Jian
• Yang Lifeng
• Wahl Michael P

Classifications

• G06F2212/466

  Metadata, control data · CPC title

• G06F2212/461

  Sector or disk block · CPC title

• G06F2212/313

  In storage device · CPC title

• G06F2212/286

  Mirrored cache memory · CPC title

• G06F2212/262

  configured as RAID · CPC title