Bandgap reference circuit

Patent metadata

Field	Value
Publication number	US-10520972-B2
Application number	US-201816195176-A
Country	US
Kind code	B2
Filing date	Nov 19, 2018
Priority date	Nov 30, 2017
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A bandgap reference (BGR) circuit is provided. The BGR circuit includes a first node, a second node, and a third node. A first resistive element is connected between the second node and the third node. The BGR circuit is operative to provide a reference voltage as an output. The BGR circuit further includes a current shunt path connected between the first node and the third node, the current shunt path being operable to regulate a voltage drop across the first resistive element.

First claim

What is claimed is:

1. A circuit, comprising:
a bandgap reference (BGR) circuit comprising a first node, a second node, a third node, and a first comparator, wherein the first comparator is operative to approximately equalize potentials of the first node and the second node, wherein a first resistive element is connected between the second node and the third node, and wherein the BGR circuit is operative to provide a reference voltage as an output; and
a current shunt path connected between the first node and the third node, wherein the current shunt path is operable to regulate a voltage drop across the first resistive element, wherein the current shunt path comprises a second comparator and a second resistive element, and wherein a first end of the second resistive element is connected to the first node and a second end of the second resistive element is connected to a first input of the second comparator.

2. The circuit of claim 1 , wherein the BGR circuit further comprises a first plurality of current sources, a first transistor, and a second transistor, wherein the first transistor is connected between the first node and the ground, wherein the second transistor is connected between the third node and the ground, and wherein the first comparator is operative to approximately equalize potentials of the first node and the second node by controlling an amount of current of the first plurality of current sources.

3. The circuit of claim 2 , wherein the current shunt path is operable to regulate the voltage drop by regulating a bias current of the second transistor.

4. The circuit of claim 3 , wherein the bias current of the second transistor is determined based on resistance values of the first resistive element and a second resistive element.

5. The circuit of claim 2 , wherein output of the first comparator is connected to a gate of each of the first plurality of current sources.

6. The circuit of claim 1 , wherein the current shunt path further comprises a second plurality of current sources, wherein an output of the second comparator is connected to a gate of each of the second plurality of current sources.

7. The circuit of claim 1 , wherein the second comparator comprises a negative feedback operational amplifier.

8. The circuit of claim 1 , wherein the current shunt path is operable to sink a first shunt current at the first node and a second shunt current at the third node.

9. The circuit of claim 8 , wherein the first shunt current is equal to the second shunt current.

10. A circuit comprising:
a bandgap reference (BGR) circuit comprising a first node, a second node, a third node, a fourth node, a first resistive element, and a first comparator, wherein the first resistive element is connected between the second node and the third node, and wherein:
the first comparator is operative to approximately equalize a potential of the first node with the potential of the second node, and
the BGR circuit is operable to provide a predetermined reference voltage at the fourth node; and

a current shunt path operable to regulate an amount of a bias current of a first transistor of the BGR circuit, wherein the first transistor is operative to sink the bias current at the third node, wherein the third node is connected to the second node, wherein the current shunt path comprises a second comparator and a second resistive element, and wherein a first end of the second resistive element is connected to the first node and a second end of the second resistive element is connected to a first input of the second comparator.

11. The circuit of claim 10 , wherein the amount of the bias current is regulated by regulating a resistance value of a first resistive element connected between the third node and the second node.

12. The circuit of claim 11 , wherein the amount of the bias current is regulated by regulating the resistance value of the first resistive element and a second resistive element of the current shunt path.

13. The circuit of claim 10 , wherein the current shunt path is operable to regulate the amount of the bias current by sinking a first shunt current at the third node.

14. The circuit of claim 10 , wherein the current shunt path is operable to regulate the amount of the bias current by sinking a first shunt current at the third node and a second shunt current at the first node, and wherein the first shunt current is approximately equal to the second shunt current.

15. The circuit of claim 10 , wherein the BGR circuit further comprises a first current source, a second current source, a third current source, and wherein the BGR circuit is operable to approximately equalize the potential of the first node with the potential of the second node by regulating a first current of the first current source, a second current of the second current source and a third current of the third current source, the first current source being operative to sink the first current at the first node, the second current source being operative to sink the second current at the second node, a third current source being operable to sink the third current at the fourth node.

16. The circuit of claim 10 , wherein the current shunt path comprises a fourth current source and a fifth current source, and wherein the fourth current source and the fifth current source are matched current sources.

17. A method for providing a reference voltage, the method comprising:
providing a bandgap reference (BGR) circuit comprising a first node, a second node, a third node, a fourth node, a first resistive element, and a first comparator, wherein the first resistive element is connected between the second node and the third node, wherein the first comparator is operative to approximately equalize potentials of the first node and the second node, and wherein the BGR circuit is operable to provide a predetermined reference voltage output at the fourth node;
injecting a first shunt current at the first node though a current shunt path;
injecting a second shunt current at the third node through the current shunt path, wherein the current shunt path comprises a second comparator and a second resistive element, and wherein a first end of the second resistive element is connected to the first node and a second end of the second resistive element is connected to a first input of the second comparator; and
regulating a bias current of a transistor of the BGR circuit by regulating at least one of the following: the first shunt current and the second shunt current.

18. The method of claim 17 , wherein the first shunt current is equal to the second shunt current.

19. The method of claim 17 , wherein regulating the bias current of the transistor comprises regulating resistance values of at least one of the following: the first resistive element connected between the second node and the third node, and the second resistive element of the current shunt path.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Horng Jaw-Juinn
• Chang Chin-Ho
• Chen Yi-Wen

Classifications

• G05F3/30 Primary

  Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities (G05F3/26 takes precedence) · CPC title

• G05F3/267 Primary

  using both bipolar and field-effect technology · CPC title