Clock screening with programmable counter-based clock interface and time-to-digital converter with high resolution and wide range operation

Patent metadata

Field	Value
Publication number	US-10520901-B2
Application number	US-201815904124-A
Country	US
Kind code	B2
Filing date	Feb 23, 2018
Priority date	Feb 23, 2018
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A subranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.

First claim

We claim:

1. A time-to-digital converter for measuring the time between a first clock edge and a second clock edge, comprising:
a slow oscillator configured to oscillate a slow oscillator output signal responsive to the first clock edge;
a coarse counter configured to count a coarse count responsive to cycles of the slow oscillator output signal;
a fast oscillator configured to oscillate a fast oscillator output signal responsive to the second clock edge;
a fine counter configured to count a fine count responsive to cycles of the fast oscillator output signal, wherein a frequency for the fast oscillator output signal is greater than a frequency for the slow oscillator output signal;
a first current source configured to sink a first current prior to the first clock edge and to not sink the first current subsequent to the first clock edge, wherein the first current is a replica of an operating current drawn by the slow oscillator; and
a second current source configured to sink a second current prior to the second clock edge and to not sink the second current subsequent to the second clock edge, wherein the second current is a replica of an operating current drawn by the fast oscillator.

2. The time-to-digital converter of claim 1 , further comprising:
a phase detector configured to latch the coarse counter responsive to a detection that a phase for the slow oscillator output signal is leading a phase for the fast oscillator output signal.

3. The time-to-digital converter of claim 2 , wherein the phase detector is further configured to latch the fine counter responsive to the detection.

4. The time-to-digital converter of claim 1 , wherein the fast oscillator is a first ring oscillator, and wherein the slow oscillator is a second ring oscillator.

5. The time-to-digital converter of claim 4 , wherein the first ring oscillator comprises a first set of at least three inverters, and wherein the second ring oscillator comprises a second set of at least three inverters.

6. The time-to-digital converter of claim 1 , further comprising:
a clock interface configured to select from a plurality of clock signals to produce the first clock edge and the second clock edge.

7. The time-to-digital converter of claim 6 , wherein the clock interface includes a down counter configured to down count a selected clock signal from the plurality of clock signals to produce the second clock edge.

8. The time-to-digital converter of claim 7 , wherein the clock interface further includes a decision logic circuit configured to enable a first selected flip-flop from a plurality of flip-flops to be clocked by the first clock edge and to enable a second selected flip-flop from the plurality of flip-flops to be clocked by the second clock edge.

9. The time-to-digital converter of claim 6 , further comprising a tuning logic circuit configured to tune a first delay circuit for delaying a first clock signal having the first clock edge responsive to a series of clock measurements.

10. A method, comprising:
oscillating a slow oscillator output signal responsive to a first clock edge for a first clock signal;
oscillating a fast oscillator output signal responsive to a second clock edge following the first clock edge, wherein a frequency for the fast oscillator output signal is greater than a frequency for the slow oscillator output signal;
counting cycles of the slow oscillator output signal to count a coarse count;
counting cycles of the fast oscillator output signal to count a fine count;
measuring a delay between the first clock edge and the second clock edge responsive to a function of the coarse count and the fine count to form a measurement of the delay;
comparing the fine count to a ratio of a frequency for the fast oscillator output signal to a frequency of the slow oscillator output signal to form a tuning code; and
delaying the first clock signal responsive to the tuning code.

11. The method of claim 10 , further comprising:
measuring a period jitter for a clock signal having the first clock edge and the second clock edge responsive to the measurement of the delay.

12. The method of claim 10 , further comprising:
measuring a K-cycle period jitter for a clock signal having the first clock edge and the second clock edge responsive to the measurement of the delay.

13. The method of claim 10 , wherein the first clock edge is a rising edge for a clock signal and the second clock edge is a falling edge for the clock signal, the method further comprising measuring a duty cycle for the clock signal responsive to the measurement of the delay.

14. The method of claim 10 , wherein the first clock edge is a clock edge for a reference clock signal, and wherein the second clock edge is a clock edge for a phase-locked loop (PLL) clock signal, the method further comprising measuring a time internal error for the PLL clock signal responsive to the measurement of the delay.

15. The method of claim 10 , wherein the first clock edge is an edge for an early clock signal and wherein the second clock edge is an edge for a late clock signal, the method further comprising measuring a clock skew between the early clock signal and the late clock signal responsive to the measurement of the delay.

Assignees

• Qualcomm Inc

Inventors

• Wu Zhengzheng
• Huang Deping
• Hinrichs Jeffrey Mark
• Pedrali-Noy Marzio

Classifications

• H03K5/26 Primary

  the characteristic being duration, interval, position, frequency, or sequence · CPC title

• G04F10/04

  by counting pulses or half-cycles of an AC {(G04F10/005 takes precedence)} · CPC title

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03K3/0315

  Ring oscillators · CPC title

• H03L7/141

  the phase-locked loop controlling several oscillators in turn · CPC title