Semiconductor device

Patent metadata

Field	Value
Publication number	US-10517176-B2
Application number	US-201815870453-A
Country	US
Kind code	B2
Filing date	Jan 12, 2018
Priority date	Mar 4, 2013
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

One semiconductor device includes a wiring substrate, a semiconductor chip, and a sealing body. The wiring substrate includes an insulating base material, a first conductive pattern formed on one surface of the insulating base material, and a second conductive pattern formed on one surface of the insulating base material, connected to the first conductive pattern and having an end face exposed to the side. The semiconductor chip is mounted on the wiring substrate so as to overlap with the first conductive pattern. The sealing body is formed on the wiring substrate so as to cover the semiconductor chip.

First claim

What is claimed is:

1. A semiconductor device comprising:
a wiring substrate having an insulating base material, a plurality of connection pads formed on a first surface of the insulating base material and disposed along at least one side of the wiring substrate;
a semiconductor chip mounted on the wiring substrate, a plurality of electrode pads disposed along at least one side of the semiconductor chip and adjacent to the side of the wiring substrate at which the plurality of connection pads are disposed;
a first conductive pattern formed on the first surface of the insulating base material, and a second conductive pattern formed on the first surface of the insulating base material and connected to the first conductive pattern, wherein:
the entire semiconductor chip overlies the first conductive pattern; and
the second conductive pattern extends continuously along a side of the wiring substrate different from the one having the connection pads;

a solder resist film covering the first surface of the insulating base material and having a plurality of openings through which the plurality of connection pads and the second conductive pattern are exposed; and
a plating layer disposed on an exposed surface of the second conductive pattern and the plurality of connection pads.

2. The semiconductor device of claim 1 , wherein the length of the second conductive pattern along the side of the wiring substrate is longer than the corresponding side of the semiconductor chip.

3. The semiconductor device of claim 1 , wherein the first conductor pattern is larger in size than the semiconductor chip.

4. The semiconductor device of claim 1 , wherein the first conductive pattern is electrically connected to one of the connection pads.

5. The semiconductor device of claim 1 , wherein the second conductive pattern is disposed along each side of the wiring substrate without any connection pads disposed therealong.

6. The semiconductor device of claim 1 , wherein the first conductive pattern is covered by the solder resist film and is free from the plating layer.

Assignees

• Longitude Semiconductor Sarl
• Longitude Licensing Ltd

Inventors

• Tomohiro Atsushi

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title