Modem and RF chips, application processor including the same and operating method thereof

Patent metadata

Field	Value
Publication number	US-10516433-B2
Application number	US-201816037024-A
Country	US
Kind code	B2
Filing date	Jul 17, 2018
Priority date	Aug 26, 2016
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

First claim

What is claimed is:

1. A modem chip for communicating with a radio frequency (RF) chip, the modem chip comprising:
a control information generator configured to generate control information for controlling a clock generator in the RF chip; and
a digital interface configured to perform digital communication with the RF chip, transmit or receive data to or from the RF chip through at least one first pin, and transmit or receive the control information to or from the RF chip through at least one second pin.

2. The modem chip of claim 1 , wherein a transmission path through the at least one first pin corresponds to a path that permits loss of information, and a transmission path through the at least one second pin corresponds to a path that does not permit loss of information.

3. The modem chip of claim 1 , further comprising:
a logic block configured to perform logic processing on data transmitted from the RF chip; and
a first clock generator configured to provide a first clock signal corresponding to a system clock signal to the logic block, wherein
the control information generator generates, as the control information, an offset control signal for compensating for a frequency offset between the first clock signal and a clock signal generated by a clock generator in the RF chip.

4. The modem chip of claim 3 , further comprising a comparator configured to compare a phase of data received from the RF chip to a phase of a signal generated in the modem chip to obtain a comparison result, and to detect the frequency offset based on the comparison result to obtain a detection result, and
wherein the control information generator generates the offset control signal according to the detection result.

5. The modem chip of claim 1 , further comprising:
a first clock generator configured to generate a first clock signal that is used in the modem chip; and
a control register configured to store setting information for adjusting a frequency of the first clock signal, wherein
update timing of the first clock generator is synchronized with update timing of the clock generator in the RF chip, depending on the control information.

6. The modem chip of claim 5 , further comprising:
a clock management unit configured to receive the first clock signal and perform a division operation on the first clock signal, wherein
timing of the division operation of the clock management unit is synchronized with timing of a division operation of a clock management unit in the RF chip, depending on the control information.

7. The modem chip of claim 1 , wherein:
the digital interface receives data having a frame structure from the RF chip, and
the data having the frame structure comprises a frame header area including information indicating a position of a channel that is active from among a plurality of channels, a subframe length area including length information of data of units of subframes which will be transmitted through the active channel, and a subframe payload area including data of each of the subframes.

8. The modem chip of claim 1 , further comprising:
a first clock generator configured to generate and provide a first clock signal to the digital interface; and
a table information storage unit configured to store table information related to a communication frequency through an antenna of the RF chip and a frequency of the first clock signal, and
wherein the first clock generator controls the frequency of the first clock signal in response to the table information according to the communication frequency applied to the RF chip.

9. The modem chip of claim 1 , further comprising:
a logic block configured to conduct logic processing on the data received from the RF chip;
a first clock generator configured to provide a first clock signal to the digital interface;
a second clock generator configured to provide a second clock signal to the logic block, the second clock signal having a lower frequency rather than the first clock signal; and
a resampler configured to provide the data received through the digital interface to the logic block and receive the first clock signal and the second clock signal, and
wherein the resampler receives the data oversampled from the RF chip in response to the first clock signal and provide the data to the logic block in response to the second clock signal.

10. The modem chip of claim 1 , further comprising:
a first clock generator configured to provide a first clock signal;
a second clock generator configured to provide a second clock signal the second clock signal having a lower frequency rather than the first clock signal; and
a mode detector configured to detect an operation mode of the modem chip,
wherein, based on the control of the mode detector, the first clock signal is provided to the digital interface in a normal mode and the second clock signal is provided to the digital interface in a low power mode.

11. An application processor comprising:
a central processing unit (CPU);
a memory configured to store programs that are executable by the CPU; and
a modem comprising a digital interface for communication with a radio frequency (RF) chip outside the application processor and a logic block for processing samples transmitted through the digital interface, wherein
the samples are transmitted from the digital interface to the logic block in synchronization with a frame synchronization signal generated based on a clock signal in the modem.

12. The application processor of claim 11 , wherein the digital interface comprises:
one or more first pins configured to transmit or receive data including the samples to or from the RF chip; and
one or more second pins configured to transmit or receive control information to or from the RF chip.

13. The application processor of claim 12 , wherein the control information comprises a synchronization signal for synchronizing one or more functional blocks in the modem with one or more functional blocks in the RF chip.

14. The application processor of claim 12 , wherein the control information comprises an offset control signal for compensating for a frequency offset between a clock generator in the modem and a clock generator in the RF chip.

15. The application processor of claim 14 , wherein the modem comprises:
a comparator configured to compare a phase of data received from the RF chip to a phase of the frame synchronization signal to obtain a comparison result, and to detect the frequency offset based on the comparison result to obtain a detection result, and
a processing unit configured to generate the offset control signal according to the detection result.

16. A radio frequency (RF) chip for communicating with modem chip, the RF chip comprising:
a logic block configured to perform logic processing on data to be transmitted to the modem chip; and
a digital interface configured to transmit the data including a plurality of samples to the modem chip, based on digital communication,
wherein the RF chip receives control information from the modem chip through the digital interface, and
wherein a frequency of a clock signal generated in the RF chip is adjusted based on the received control information.

17. The RF chip of claim 16 , wherein the control information comprises a synchronization signal for synchronizing one or more functional blocks in the RF chip with one or more functional blocks in the modem chip,
wherein the RF chip further comprises a first clock generator configured to provide a first clock signal to the logic block, and
wherein update timing of the first cloc

Assignees

• Samsung Electronics Co Ltd

Inventors

• Huh Jun-Ho
• Jang Ho-Rang
• Kim Seok-Chan
• Kang In-Tae
• Lee Sang-Heon
• Chae Kwan-Yeob
• Lee June-Hee
• Park Sang-Hune
• Lee Jae-Chol
• LEE Hyung-kweon

Classifications

• H04J3/0685

  Clock or time synchronisation in a node; Intranode synchronisation · CPC title

• H04L7/04

  Speed or phase control by synchronisation signals {(H04L7/0075 takes precedence)} · CPC title

• H04L27/2655

  Synchronisation arrangements · CPC title

• H04L27/2656 Primary

  Frame synchronisation, e.g. packet synchronisation, time division duplex [TDD] switching point detection or subframe synchronisation · CPC title

• H03M3/00

  Conversion of analogue values to or from differential modulation · CPC title