3D-printed protective shell structures for stress sensitive circuits

US10516381B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10516381-B2
Application numberUS-201715858892-A
CountryUS
Kind codeB2
Filing dateDec 29, 2017
Priority dateDec 29, 2017
Publication dateDec 24, 2019
Grant dateDec 24, 2019

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In one aspect of the disclosure, a semiconductor package is disclosed. The semiconductor package includes a lead frame. A semiconductor die is attached to a first side of the lead frame. A protective shell covers at least a first portion of the first surface of the semiconductor die. The protective shell comprises of ink residue. A layer of molding compound covers an outer surface of the protective shell and exposed portion of the first surface of the semiconductor die. A cavity space is within an inner space of the protective shell and the first portion of the top surface of the semiconductor die.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor package, comprising: a lead frame having a first side; a semiconductor die attached to the first side of the lead frame, wherein the semiconductor die includes a first surface; a shell comprising ink residue covering at least a first portion of the first surface of the semiconductor die; a layer of molding compound covering an outer surface of the shell and a second portion of the first surface of the semiconductor die; and a cavity space between an inner surface of the shell and the first portion of the first surface of the semiconductor die. 2. The semiconductor package of claim 1 , wherein the shell is shaped as at least one of a rounded edge cuboid and a geodesic dome. 3. The semiconductor package of claim 1 , wherein the cavity space is filled with at least one of an inert gas, air, and thermal grease. 4. The semiconductor package of claim 1 , wherein the first portion of the first surface of the semiconductor die is less than an entire first surface of the semiconductor die. 5. The semiconductor package of claim 1 , wherein the shell is made from one of a metal, ceramic, and thermoplastic. 6. The semiconductor package of claim 1 , wherein the shell further comprises one or more support columns. 7. The semiconductor package of claim 6 , wherein the one or more support columns are formed to conduct heat from the semiconductor die. 8. A semiconductor package, comprising: an interposer having a first side and a second side; a substrate attached to the second side of the interposer; a semiconductor die attached to the first side of the interposer, wherein an exposed surface of the first side of the interposer is not covered by the semiconductor die; a shell comprising ink residue on the exposed surface of the interposer, wherein the shell covers a first surface of the semiconductor die; at least one support structure contacting the shell and the first surface of the semiconductor die; and a layer of molding compound covering an outer surface of the shell and a remaining portion of the exposed surface of the first side of the interposer. 9. The semiconductor package of claim 8 , wherein the shell is shaped as at least one of a rounded edge cuboid and a geodesic dome. 10. The semiconductor package of claim 8 further comprising a cavity formed between an inner space of the shell and the first surface of the semiconductor die covered by the shell, wherein the cavity is filled with at least one of an inert gas, air, and thermal grease. 11. The semiconductor package of claim 10 , wherein the at least one support structure is within the cavity. 12. The semiconductor package of claim 8 , wherein the semiconductor die is electrically connected to the interposer, and the interposer is electrically connected to the substrate. 13. The semiconductor package of claim 8 , wherein the shell is made from one of a metal, ceramic, and thermoplastic. 14. The semiconductor package of claim 8 , wherein the at least one support structure is formed on the top surface of the semiconductor die. 15. A semiconductor package comprising: a semiconductor die having a first surface; a shell comprising ink residue covering a first portion of the first surface of the semiconductor die, wherein the shell creates a hermetic seal with the first surface of the semiconductor die; and at least one support structure contacting the shell and the first surface of the semiconductor die, wherein the first portion of the semiconductor die is less than an entire surface of the first surface of the semiconductor die. 16. The semiconductor package of claim 15 , wherein the shell is formed by printable material. 17. The semiconductor package of claim 15 , wherein the shell is shaped as at least one of a rounded edge cuboid and a geodesic dome. 18. The semiconductor package of claim 15 , wherein the shell is made from one of a metal, ceramic, and thermoplastic. 19. The semiconductor package of claim 15 , wherein an area within the hermetic seal is filled with at least one of an inert gas, air, and thermal grease.

Assignees

Inventors

Classifications

  • using printing, e.g. ink-jet printing · CPC title

  • carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC · CPC title

  • Cross-sectional shapes (H10W70/481 takes precedence) · CPC title

  • Fillings · CPC title

  • the encapsulations having cavities other than that occupied by chips · CPC title

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Frequently asked questions

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What does patent US10516381B2 cover?
In one aspect of the disclosure, a semiconductor package is disclosed. The semiconductor package includes a lead frame. A semiconductor die is attached to a first side of the lead frame. A protective shell covers at least a first portion of the first surface of the semiconductor die. The protective shell comprises of ink residue. A layer of molding compound covers an outer surface of the protec…
Who is the assignee on this patent?
Texas Instruments Inc
What technology area does this patent fall under?
Primary CPC classification H10W70/468. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 24 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).