Semiconductor chip stack with identification section on chip side-surfaces for stacking alignment

Patent metadata

Field	Value
Publication number	US-10515932-B2
Application number	US-201414900067-A
Country	US
Kind code	B2
Filing date	Jun 13, 2014
Priority date	Jun 21, 2013
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

This semiconductor device is formed by stacking a plurality of semiconductor chips that each have a plurality of bump electrodes, each of the plurality of semiconductor chips being provided with an identification section formed on a respective side face. Each semiconductor chip has a similar arrangement for its respective plurality of bump electrodes, and each identification section is formed so that the positional relationship with a respective reference bump electrode provided at a specific location among the respective plurality of bump electrodes is the same in each semiconductor chip. The plurality of semiconductor chips are stacked such that the bump electrodes provided thereon are electrically connected in the order of stacking of the semiconductor chips, while the side faces on which the identification sections are formed are oriented in the same direction.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of semiconductor chips each having a plurality of bump electrodes, wherein the plurality of semiconductor chips are stacked, and wherein:
each semiconductor chip of the plurality of semiconductor chips comprises a semiconductor substrate and only one identification section formed of an insulating member on each side surface of the semiconductor substrate, wherein each identification section comprises two lines of a first material sandwiching a portion of the semiconductor substrate, each line of the first material is formed through an entire thickness of the semiconductor substrate, and the first material is different from the semiconductor substrate;
the plurality of bump electrodes are arranged in a same way on each of the plurality of semiconductor chips,
wherein the plurality of bump electrodes on each of the plurality of semiconductor chips comprise a reference bump electrode provided at a specific location, and the identification sections are formed on each of the plurality of semiconductor chips in such a way as to have a same positional relationship with the reference bump electrode; and
the plurality of semiconductor chips are stacked in such a way that the bump electrodes provided thereon are electrically connected in the stacking order of the semiconductor chips and in such a way that the side surfaces on which the identification sections are formed are oriented in a same direction.

2. The semiconductor device as claimed in claim 1 , wherein a structure lying across adjacent semiconductor chips defined by a dicing area is formed on a wafer in which the semiconductor chips are formed, and the identification section is formed by dicing the dicing area.

3. The semiconductor device as claimed in claim 2 , wherein the structure is formed with a circular shape.

4. The semiconductor device as claimed in claim 2 , wherein the structure is formed with a linear shape orthogonal to a dicing line.

5. The semiconductor device as claimed in claim 2 , wherein the structure is formed by filling a trench formed in a substrate of the semiconductor chip with the insulating member.

6. The semiconductor device as claimed in claim 1 , wherein the identification section is formed by a wiring pattern in a circuit-formation layer of the semiconductor chip.

7. A semiconductor device comprising:
a first semiconductor chip comprising:
a first main surface;
a second main surface opposite the first main surface;
a first side surface joining the first main surface and the second main surface,

wherein a semiconductor substrate is on the first side surface;
a first bump electrode formed on the first main surface; and
a first identification section corresponding to the first bump electrode, wherein the first identification section is the only identification section formed of an insulating member on the first side surface, the first identification section comprising two lines of a first material sandwiching a portion of the semiconductor substrate, each line of the first material is formed through an entire thickness of the semiconductor substrate, and the first material is different from the semiconductor substrate; and

a second semiconductor chip comprising:
a third main surface;
a fourth main surface opposite the third main surface;
a second side surface joining the third main surface and the fourth main surface;
a second bump electrode corresponding to the first bump electrode, wherein the second bump electrode is formed on the third main surface;
a third bump electrode electrically connected to the second bump electrode, wherein the third bump electrode is formed on the fourth main surface; and
a second identification section formed on the second side surface with a same positional relationship with respect to the second bump electrode as a positional relationship between the first bump electrode and the first identification section, said second semiconductor chip being stacked on the first semiconductor chip in such a way that the second bump electrode is configured to be connected to the first bump electrode and the first side surface and the second side surface are oriented in a same direction.

Assignees

• Ps4 Luxco Sarl
• Longitude Licensing Ltd

Inventors

• Tsuji Daisuke

Classifications

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title