Package system for integrated circuits

Patent metadata

Field	Value
Publication number	US-10515829-B2
Application number	US-201715425282-A
Country	US
Kind code	B2
Filing date	Feb 6, 2017
Priority date	May 26, 2010
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

A package system comprising a first interconnect structure arranged over a first surface of a first substrate; a plurality of first through silicon via (TSV) structures in and extending through the first substrate; a molding compound material surrounding the first substrate; at least one through via in the molding compound material with the through via being offset from the first substrate in a direction parallel to the first surface; a second interconnect structure over a second surface of the first substrate; and a first integrated circuit mounted over the first surface of the substrate, with the first integrated circuit being electrically coupled to at least one of the first TSV structures through the first interconnect structure and a connecting bump while the first interconnection structure is electrically coupled to the through via. The first interconnect structure may also be configured for mounting one or more integrated circuits and/or a second interposer on a surface opposite that of the first interposer.

First claim

What is claimed is:

1. A package system comprising:
a first substrate;
a first interconnect structure over a first surface of the first substrate;
a plurality of first through silicon via (TSV) structures in the first substrate;
a molding compound material surrounding the first substrate;
a through via in the molding compound material, wherein the through via is offset from the first substrate in a direction parallel to the first surface;
a second interconnect structure on a second surface of the first substrate opposite the first interconnect structure; and
a first integrated circuit over the first surface of the first substrate,
wherein the first integrated circuit is electrically coupled to at least a first TSV structure of the plurality of first TSV structures by the first interconnect structure and a connecting bump, and
wherein the first interconnect structure is electrically coupled to the through via.

2. The package system according to claim 1 , wherein:
the first substrate has a first coefficient of thermal expansion (CTE 1 );
the first integrated circuit has a second coefficient of thermal expansion (CTE 2 ); and
CTE 1 and CTE 2 are substantially equal.

3. The package system according to claim 2 , further comprising:
a second integrated circuit over the first substrate, the second integrated circuit having a third coefficient of thermal expansion (CTE 3 );
wherein the second integrated circuit is electrically coupled with at least a second TSV structure of the plurality of first TSV structures, and
CTE 1 and CTE 3 are substantially equal.

4. The package system according to claim 1 , wherein:
the molding compound material has a first surface facing the first integrated circuit,
the first interconnect structure has a first surface facing the first integrated circuit, and
the first surface of the molding compound material is coplanar with the first surface of the first interconnect structure.

5. The package system according to claim 1 , wherein:
the first interconnect structure has a first metallic line pitch LP 1 ;
the second interconnect structure has a second metallic line pitch LP 2 greater than LP 1 .

6. The package system according to claim 1 , wherein:
the through via is electrically coupled to both the first interconnect structure and the second interconnect structure.

7. The package system according to claim 1 , wherein:
the molding compound material includes a spacing region between the second interconnect structure and the second surface of the first substrate; and
wherein the plurality of first TSV structures extend through the spacing region.

8. The package system according to claim 1 , further comprising:
an interposer between the first integrated circuit and the first substrate, wherein
the interposer comprises a plurality of second TSV structures, and
wherein at least one second TSV structure of the plurality of second TSV structures is electrically coupled with both the first integrated circuit and at least one first TSV structure of the plurality of first TSV structures.

9. The package system according to claim 5 , further comprising:
a third interconnect structure between the second surface of the first substrate and the second interconnect structure.

10. The package system according to claim 9 , wherein:
the third interconnect structure has a third metallic line pitch LP 3 , and further wherein LP 2 >LP 3 >LP 1 .

11. The package system according to claim 1 , wherein:
the molding compound material has a first surface opposite the first integrated circuit, and
the first surface of the molding compound material is coplanar with a surface of at least one TSV structure of the plurality of first TSV structures.

12. The package system according to claim 1 , wherein a maximum height of the molding compound in a direction perpendicular to the first surface of the substrate is greater than a height of the through via.

13. The package system according to claim 1 , wherein a height of the through via is substantially equal to a height at least one first TSV structure of the plurality of first TSV structures.

14. The package system according to claim 1 , wherein at least one first TSV structure of the plurality of first TSV structures comprises:
a barrier material; and
a conductive material, wherein the barrier material surrounds the conductive material.

15. The package system according to claim 1 , wherein the molding compound contacts a sidewall of the first interconnect structure.

16. The package system according to claim 1 , wherein a length of the second interconnect structure in the direction parallel to the first surface is greater than a length of the substrate in the direction parallel to the first surface.

17. The package system according to claim 1 , wherein a length of the second interconnect structure in the direction parallel to the first surface is greater than a length of the first interconnect structure in the direction parallel to the first surface.

18. The package system according to claim 1 , wherein a material of the through via is a same material as a material of at least one first TSV structure of the plurality of first TSV structures.

19. The package system according to claim 1 , further comprising a second integrated circuit electrically connected to the first interconnect structure.

20. The package system according to claim 1 , wherein at least one first TSV structure of the plurality of first TSV structures is electrically connected to the second interconnect structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Wei-Cheng
• Hou Shang-Yun
• Jeng Shin-Puu
• Yu Chen-Hua

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title