Methods for repairing substrate lattice and selective epitaxy processing

Patent metadata

Field	Value
Publication number	US-10515799-B2
Application number	US-201816046717-A
Country	US
Kind code	B2
Filing date	Jul 26, 2018
Priority date	May 24, 2018
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

The present disclosure describes patterned devices and methods for repairing substrate lattice damage in a patterned device. The patterned device includes a substrate, an alternating conductor and dielectric stack atop the substrate, a channel hole extending through the alternating conductor and dielectric stack to the substrate, and an epitaxial grown layer at a bottom of the channel hole and a top surface of the substrate. A part of the substrate in contact with the epitaxial grown layer has a dopant or doping concentration different from an adjacent part of the substrate. The method includes forming a channel hole in an insulating layer atop a substrate, forming an amorphous layer in a top side of the substrate below the channel hole, heating to crystallize the amorphous layer, and growing an epitaxial layer on the crystallized layer in the channel hole.

First claim

What is claimed is:

1. A method for repairing substrate lattice damage in a patterned device, the method comprising:
forming a channel hole in an insulating layer atop a substrate;
forming an amorphous layer in a top side of the substrate below the channel hole;
heating to crystallize the amorphous layer; and
growing an epitaxial layer on the crystallized layer in the channel hole.

2. The method of claim 1 , wherein forming the channel hole comprises using an anisotropic reactive ion etch.

3. The method of claim 1 , further comprising cleaning the channel hole after the channel hole is formed, wherein cleaning the channel hole comprises a process selected from the group consisting of plasma etching, hydrogen chloride etching, and hydrogen fluoride etching.

4. The method of claim 1 , wherein forming the amorphous layer comprises ion implantation.

5. The method of claim 4 , wherein a total dosage of the implantation is greater than 5-10 15 ion/cm 3 .

6. The method of claim 4 , wherein an implant temperature is −100° C. to 23° C.

7. The method of claim 4 , wherein an implant energy is 25 keV to 250 keV.

8. The method of claim 4 , wherein an implanted material comprises one or more of III element, IV element, V element, and inert element.

9. The method of claim 8 , wherein the implanted material comprises one or more of silicon, carbon, boron, phosphorus, germanium, and argon.

10. The method of claim 4 , wherein ion implantation comprises multiple sub-processes.

11. The method of claim 10 , wherein the multiple sub-processes comprise a first sub-process and a second sub-process, wherein in the first sub-process, one or more of III element is implanted with a comparatively lower energy, and wherein in the second sub-process, one or more of V element is implanted with a comparatively higher energy.

12. The method of claim 1 , wherein heating the amorphous layer comprises annealing.

13. The method of claim 12 , wherein annealing comprises a temperature of 600° C. to 800° C.

14. The method of claim 12 , wherein annealing comprises a duration of 20 sec to 200 sec.

15. The method of claim 1 , wherein the insulating layer comprises alternating first and second insulating layers.

16. A method of repairing substrate lattice damage in a patterned device, the method comprising:
forming a channel hole in an alternating dielectric stack atop a substrate;
forming an amorphous layer in the substrate by ion implantation through the channel hole;
transforming the amorphous layer to a crystallized layer by crystallizing the amorphous layer through solid-phase epitaxy; and
growing an epitaxial layer with the crystallized layer as a seed layer.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Wang Xiao Jun
• Zhou Wei
• Xu lin kang
• Li Guan Nan

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P30/209

  in silicon to make buried insulating layers · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/36

  characterised by treatments done before the formation of the materials · CPC title