Multilayer ceramic capacitor

Patent metadata

Field	Value
Publication number	US-10515765-B2
Application number	US-201916391861-A
Country	US
Kind code	B2
Filing date	Apr 23, 2019
Priority date	Nov 4, 2016
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

A multilayer ceramic capacitor includes a body in which a plurality of dielectric layers are stacked, first and second external electrodes disposed on one surface of the body and spaced apart from each other, a plurality of first and second internal electrodes opposing each other, the dielectric layers being interposed therebetween, a first conductive via connecting the plurality of first internal electrodes to the first external electrode, a second conductive via connecting the plurality of second internal electrodes to the second external electrode, and a shielding layer covering at least a portion of an external surface of the body.

First claim

What is claimed is:

1. A multilayer ceramic capacitor, comprising:
a body in which a plurality of dielectric layers are stacked;
first and second external electrodes disposed on one surface of the body and spaced apart from each other;
a plurality of first and second internal electrodes opposing each other, the dielectric layers being interposed therebetween;
a first conductive via directly connecting the plurality of first internal electrodes to the first external electrode;
a second conductive via directly connecting the plurality of second internal electrodes to the second external electrode;
a third conductive via directly connected to one of the plurality of first internal electrodes which are connected to the first conductive via;
a fourth conductive via directly connected to one of the plurality of second internal electrodes which are connected to the second conductive via; and
a shielding layer covering at least a portion of an external surface of the body,
wherein the third conductive via is shorter than the first conductive via, and the fourth conductive via is shorter than the second conducive via.

2. The multilayer ceramic capacitor of claim 1 , wherein the first and second external electrodes are disposed on a bottom surface of the body, and
the shielding layer is disposed on end surfaces and a top surface of the body.

3. The multilayer ceramic capacitor of claim 1 , further comprising a first insulating layer disposed between the shielding layer and the body.

4. The multilayer ceramic capacitor of claim 1 , further comprising a second insulating layer disposed on the shielding layer.

5. The multilayer ceramic capacitor of claim 1 , wherein the shielding layer is any one selected from the group consisting of a metal shielding layer formed of one metal selected from aluminum (Al), copper (Cu), nickel (Ni) and silver (Ag), a carbon-based shielding layer, a conductive polymer based shielding layer, a Ni—Cu—Ni plated conductive fabric, and a Ni—Cu—Ni—Au plated conductive fabric, or a combination thereof.

Assignees

• Samsung Electro Mech

Inventors

• Chong Won Sik
• Jang Young Su

Classifications

• H01G4/232

  electrically connecting two or more layers of a stacked or rolled capacitor · CPC title

• H01G4/12

  Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

• H01G4/224

  Housing; Encapsulation · CPC title

• H01G2/06

  specially adapted for mounting on a printed-circuit support · CPC title

• H01G2/22 Primary

  Electrostatic or magnetic shielding · CPC title