Memory device, operating method thereof, and operating method of memory system including the same

Patent metadata

Field	Value
Publication number	US-10515675-B2
Application number	US-201715650460-A
Country	US
Kind code	B2
Filing date	Jul 14, 2017
Priority date	Nov 30, 2016
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

A method for operating a memory device includes: receiving a write command; checking out whether a data strobe signal toggles or not after a given time passes from a moment when the write command is received; when the data strobe signal is checked out to be maintained at a uniform level, detecting voltage levels of a plurality of data pads; and performing an operation that is selected based on the voltage levels of the plurality of the data pads among a plurality of predetermined operations.

First claim

What is claimed is:

1. A memory device comprising:
a strobe toggle sensing circuit suitable for sensing whether or not a data strobe signal toggles when data is received within a time period equal to a write latency from when a write command is applied;
a serial-to-parallel converting circuit suitable for, when a toggling of the data strobe signal is sensed, performing a serial-to-parallel conversion onto data that are received through a plurality of data pads to produce parallel data, and transferring the parallel data to a memory core; and
a pattern generating circuit suitable for, when the toggling of the data strobe signal is not sensed, transferring a data pattern that is selected based on voltage levels of the plurality of the data pads, from a plurality of data patterns, to the memory core.

2. The memory device of claim 1 , wherein the strobe toggle sensing circuit applies the data strobe signal as an input strobe signal when the toggling of the data strobe signal is sensed, and applies a clock as the input strobe signal when the toggling of the data strobe signal is not sensed.

3. The memory device of claim 2 , further comprising:
a plurality of data receiving circuits suitable for receiving data from the plurality of the data pads in synchronization with the input strobe signal.

4. The memory device of claim 3 , further comprising:
a clock receiving circuit suitable for receiving the clock.

5. The memory device of claim 1 , wherein the strobe toggle sensing circuit senses whether or not the data strobe signal toggles after a given time passes from the write command.

6. The memory device of claim 5 , wherein the given time includes a write latency.

7. A memory system comprising:
a memory device; and
a memory controller suitable for controlling the memory device,
wherein the memory device comprises:
a strobe toggle sensing circuit suitable for sensing whether or not a data strobe signal transferred from the memory controller toggles when data is received within a time period equal to a write latency from when a write command is applied;
a serial-to-parallel converting circuit suitable for, when a toggling of the data strobe signal is sensed, performing a serial-to-parallel conversion onto data that are transferred from the memory controller through a plurality of data pads to produce parallel data, and transferring the parallel data to a memory core; and

a pattern generating circuit suitable for, when the toggling of the data strobe signal is not sensed, transferring a data pattern that is selected based on voltage levels of the plurality of the data pads, from a plurality of data patterns, to the memory core.

8. The memory system of claim 7 , wherein the strobe toggle sensing circuit applies the data strobe signal as an input strobe signal when the toggling of the data strobe signal is sensed, and applies a clock as the input strobe signal when the toggling of the data strobe signal is not sensed, and
wherein the memory device further comprises:
a plurality of data receiving circuits suitable for receiving data from the plurality of the data pads in synchronization with the input strobe signal.

9. The memory system of claim 7 , wherein the strobe toggle sensing circuit senses whether or not the data strobe signal toggles after a given time passes from the write command.

10. The memory system of claim 9 , wherein the given time includes a write latency.

Assignees

• Sk Hynix Inc

Inventors

• JO Sang-Gu
• Lee Sung-Eun
• Kwon Jung-Hyun

Classifications

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/22 Primary

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title