Memory apparatus with redundancy array

Patent metadata

Field	Value
Publication number	US-10514983-B2
Application number	US-201715498071-A
Country	US
Kind code	B2
Filing date	Apr 26, 2017
Priority date	Apr 26, 2017
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

Apparatuses and methods for memory repair for a memory device are described. An example apparatus includes: a data input/output circuit that provides data via a plurality of data signal lines; memory cell arrays; an ECC/Parity redundancy array; and a redundancy circuit coupled to the plurality of data signal lines. The redundancy circuit includes an error correction block that generates error correction information based on the data and provides the error correction information to the ECC/Parity redundancy array. If during test it is determined that a failure is not repairable by standard redundancy including error correction code, the error correction parity array is not needed and can be redirected by a block repair circuit. The error correction circuit can now have its functionality changed to allow the error correction array to become a block repair.

First claim

What is claimed is:

1. An apparatus comprising:
a plurality of data terminals;
at least one memory cell array that includes a plurality of memory cells;
an ECC/parity redundancy array that includes a plurality of memory cells; and
a redundancy circuit configured to communicate data with the data terminals and further configured to provide the data to the at least one memory cell array and the ECC/parity redundancy array and to receive the data from the at least one memory cell array and the ECC/parity redundancy array,
wherein the redundancy circuit is configured to provide a portion of the data received from the plurality of data terminals to the ECC/parity redundancy array and further configured to receive the portion of the data from the ECC/parity redundancy array and to provide the portion of the data responsive to a first state of a control signal,
wherein the redundancy circuit is configured to provide error correction information to the ECC/parity redundancy array and further configured to receive the error correction information from the ECC/parity redundancy array responsive to a second state of the control signal that is different from the first state of the control signal,
wherein the redundancy circuit comprises a block repair circuit configured to prevent an error in the data responsive to the first state of the control signal,
wherein the block repair circuit is configured to replace a plurality of defective memory cells in a block in a test mode, and further configured to activate a block repair if a number of the defective memory cells is beyond error correction capability of the redundancy circuit,
wherein the block is in one array of the memory cell arrays, and
wherein data designated to the one array and data designated to memory cell arrays between the one array and the ECC/parity redundancy array are directed to an adjacent array in a direction towards the ECC/parity redundancy array.

2. The apparatus of claim 1 , wherein the block repair circuit further comprises a fuse circuit configured to provide the control signal.

3. An apparatus comprising:
a plurality of data terminals;
at least one memory cell array that includes a plurality of memory cells;
an ECC/parity redundancy array that includes a plurality of memory cells; and
a redundancy circuit configured to communicate data with the data terminals and further configured to provide the data to the at least one memory cell array and the ECC/parity redundancy array and to receive the data from the at least one memory cell array and the ECC/parity redundancy array,
wherein the redundancy circuit is configured to provide a portion of the data received from the plurality of data terminals to the ECC/parity redundancy array and further configured to receive the portion of the data from the ECC/parity redundancy array and to provide the portion of the data responsive to a first state of a control signal,
wherein the redundancy circuit is configured to provide error correction information to the ECC/parity redundancy array and further configured to receive the error correction information from the ECC/parity redundancy array responsive to a second state of the control signal that is different from the first state of the control signal,
wherein the redundancy circuit comprises a block repair circuit configured to prevent an error in the data responsive to the first state of the control signal,
wherein the block repair circuit is configured to replace a plurality of defective memory cells in a block in a test mode, and further configured to activate a block repair if a number of the defective memory cells is beyond error correction capability of the redundancy circuit,
wherein the block repair circuit further comprises a fuse circuit configured to provide the control signal,
wherein the fuse circuit is configured to provide fuse signals relevant to selection information, and
wherein the block repair circuit is configured to receive compare signals related to the selection information and a destination cell address, to compare the compare signals with at least a portion of defective address information, and further configured to enable an access operation with a redundant row in the ECC/parity redundancy array associated with a row including the destination cell address in the memory cell array.

4. An apparatus comprising:
a data input/output circuit coupled between a plurality of data terminals and a plurality of data signal lines, configured to receive data from the plurality of data terminals and further configured to provide the data via the plurality of data signal lines;
at least one memory cell array that includes a plurality of memory cells;
an ECC/parity redundancy array that includes a plurality of memory cells; and
a redundancy circuit coupled to the data input/output circuit via the plurality of data signal lines, comprising:
an error correction block configured to generate error correction information based on the data from the data input/output circuit and further configured to provide the error correction information to the ECC/parity redundancy array, responsive to a first state of a control signal; and
a block repair circuit configured to redirect a first portion of the data from the data input/output circuit designated to a first block in a first array including a plurality of defective cells, among the at least one memory cell array, to a second block different from the first block, responsive to a second state of the control signal, based on address information of the block,

wherein the second block is in a second array that is different from the first array, and
wherein the block repair circuit configured to redirect a second portion of the data from the data input/output circuit to the ECC/parity redundancy array.

5. The apparatus of claim 4 , wherein the second portion of the data is the first portion of the data, and
wherein the second array is the ECC/parity redundancy array.

6. The apparatus of claim 4 , wherein the second array is adjacent to the first array in a direction towards the ECC/parity redundancy array, and
wherein the block repair circuit is further configured to redirect data designated to memory cell arrays between the first array and the ECC/parity redundancy array to adjacent arrays respectively in the direction towards the ECC/parity redundancy array.

7. The apparatus of claim 6 , wherein the redundancy circuit further comprises a remapping circuit configured to provide data from the plurality of data signal lines to each array of the memory cell arrays and the ECC/parity redundancy array via a plurality of local data buses for writing and further configured to provide data from each array of the memory cell arrays and the ECC/parity redundancy array via a plurality of local data buses for reading to the plurality of data signal lines.

8. The apparatus of claim 7 , wherein the remapping circuit comprises:
a plurality of first multiplexers, wherein each first multiplexer is coupled between one data signal line among the plurality of data signal lines and a pair of local data buses for writing, the pair of local data buses for writing including one local data bus coupled to a memory cell array corresponding to the one data signal line and the other local data bus coupled to an adjacent array; and
a plurality of second multiplexers, wherein each second multiplexer is coupled between the one data signal line among the plurality of data signal lines and a pair of local data buses for reading, the pair of local data buses for reading including one local data bus coupled to a memory cell array corresponding to the one data signal line and the other local data bus coupled to an adjacent array, and
wherein the remapping cir

Assignees

• Micron Technology Inc

Inventors

• Eichmeyer Seth
• Rehmeyer James
• Johnson Benjamin
• Johnson Jason

Classifications

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C29/76

  using address translation or modifications · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title