Preventing duplicate execution by sharing a result between different processing lanes assigned micro-operations that generate the same result

Patent metadata

Field	Value
Publication number	US-10514928-B2
Application number	US-201514663858-A
Country	US
Kind code	B2
Filing date	Mar 20, 2015
Priority date	Apr 17, 2014
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

A data processing apparatus has control circuitry for detecting whether a first micro-operation to be processed by a first processing lane would give the same result as a second micro-operation processed by a second processing lane. If they would give the same result, then the first micro-operation is prevented from being processed by the first processing lane and the result of the second micro-operation is output as the result of the first micro-operation. This avoids duplication of processing, to save energy for example.

First claim

The invention claimed is:

1. A data processing apparatus comprising:
first and second processing lanes configured to perform data processing operations in parallel in response to micro-operations; and
control circuitry configured to detect whether a first micro-operation to be processed by the first processing lane would give the same result as a second micro-operation to be processed in parallel with the first micro-operation by the second processing lane in dependence on operands specified by the first micro-operation and the second micro-operation and on operation identifiers indicating a data processing operation to be performed on the operands in response to each of the first micro-operation and the second micro-operation;
said control circuitry comprising an operation identifier comparator to compare said operation identifiers;
wherein if the control circuitry detects that the first micro-operation would give the same result as the second micro-operation, then the control circuitry is configured to prevent the first micro-operation from being processed by the first processing lane and to control the first processing lane to output the result of the second micro-operation as the result of the first micro-operation.

2. The data processing apparatus according to claim 1 , comprising a result path configured to provide the result of the second micro-operation generated by the second processing lane to an output of the first processing lane.

3. The data processing apparatus according to claim 1 , wherein the control circuitry is configured to detect that the first micro-operation would give the same result as the second micro-operation if one of the first micro-operation and the second micro-operation can be translated into the other of the first micro-operation and the second micro-operation.

4. The data processing apparatus according to claim 1 , wherein the control circuitry is configured to prevent the first processing lane from processing the first micro-operation by placing at least part of the first processing lane in a power saving state during a processing cycle when said at least part of the first processing lane would otherwise be processing the first micro-operation.

5. The data processing apparatus according to claim 1 , wherein the control circuitry is configured to prevent the first processing lane from processing the first micro-operation by preventing the first micro-operation from being passed to the first processing lane.

6. The data processing apparatus according to claim 1 , wherein the second micro-operation comprises the micro-operation received for processing by the second processing lane in the same cycle as the first micro-operation is received for processing by the first processing lane.

7. The data processing apparatus according to claim 1 , wherein the second micro-operation comprises the last valid micro-operation received for processing by the second processing lane.

8. The data processing apparatus according to claim 1 , wherein the second micro-operation comprises an earlier micro-operation processed by the second processing lane.

9. The data processing apparatus according to claim 1 , wherein the control circuitry is configured to detect whether the first micro-operation would give the same result as an earlier micro-operation processed by the first processing lane; and
if the control circuitry detects that the first micro-operation would give the same result as the earlier micro-operation processed by the first processing lane, then the control circuitry is configured to prevent the first micro-operation from being processed by the first processing lane and to control the first processing lane to output the result of the earlier micro-operation processed by the first processing lane as the result of the first micro-operation.

10. The data processing apparatus according to claim 1 , comprising a table configured to store at least one table entry for identifying an earlier micro-operation processed by one of the first and second processing lanes and a result of the earlier micro-operation;
wherein the control circuitry is configured to perform a first table lookup to detect whether the table stores a corresponding table entry identifying an earlier micro-operation which would give the same result as the first micro-operation; and
if the table stores the corresponding table entry, then the control circuitry is configured to prevent the first micro-operation from being processed by the first processing lane, and to control the first processing lane to output the result stored in the corresponding table entry as the result of the first micro-operation.

11. The data processing apparatus according to claim 10 , wherein the control circuitry is configured to update the table with results of micro-operations generated by both the first processing lane and the second processing lane.

12. The data processing apparatus according to claim 10 , wherein the control circuitry is configured to perform a second table lookup to detect whether the table stores a matching table entry identifying an earlier micro-operation which would give the same result as a current micro-operation to be processed by the second processing lane; and
if the table stores the matching table entry, then the control circuitry is configured to prevent the current micro-operation from being processed by the second processing lane, and to control the second processing lane to output the result stored in the matching table entry as the result of the current micro-operation.

13. The data processing apparatus according to claim 10 , wherein if the control circuitry detects that the first micro-operation would give the same result as the micro-operation received for processing by the second processing lane in the same cycle as the first micro-operation is received for processing by the first processing lane, then the control circuitry is configured to omit the first table lookup.

14. The data processing apparatus according to claim 1 , comprising filtering circuitry configured to detect whether the first micro-operation satisfies at least one predetermined condition;
wherein if the filtering circuitry detects that the first micro-operation does not satisfy the at least one predetermined condition, then the control circuitry is configured to pass the first micro-operation for processing by the first processing lane without detecting whether the first micro-operation would give the same result as the second micro-operation.

15. The data processing apparatus according to claim 1 , wherein the micro-operations received for processing by the first and second processing lanes in the same processing cycle correspond to instances of the same program instruction identified by a common program counter shared between the first and second processing lanes, with the operands for the micro-operations specified independently for each of the first and second processing lanes.

16. The data processing apparatus according to claim 1 , wherein the operands comprise a plurality of data elements, the first and second processing lanes using respective data elements of the operands.

17. The data processing apparatus according to claim 1 , comprising N processing lanes configured to perform data processing operations in response to micro-operations, where N>2;
wherein the N processing lanes comprise two or more subsets of processing lanes, each subset comprising fewer than N processing lanes; and
the first and second processing lanes are processing lanes within the same subset.

18. The data proce

Assignees

• Advanced Risc Mach Ltd

Inventors

• Sideris Isidoros
• Croxford Daren
• Burdass Andrew

Classifications

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F9/3826

  Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage · CPC title

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F1/329

  by task scheduling · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title