Metastable true random number generator realized on FPGA

Patent metadata

Field	Value
Publication number	US-10514894-B2
Application number	US-201816045688-A
Country	US
Kind code	B2
Filing date	Jul 25, 2018
Priority date	Nov 17, 2017
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

A metastable true random number generator realized on an FPGA comprises a configurable delay chain including rough adjustment module and a fine adjustment module. The rough adjustment module comprises 32 rough adjustment cells each including a 1st 6-input lookup table and a two-to-one selector. The 1st input port of each 1st 6-input lookup table is connected to the 1st input terminal of the corresponding two-to-one selector, and the connecting terminal is the input terminal of the corresponding rough adjustment cell. The 2nd input port, the 3rd input port, the 4th input port, the 5th input port and the 6th input port of each 1st 6-input lookup table are all accessed to a low level 0. The output port of each 1st 6-input lookup table is connected to the 2nd input terminal of the corresponding two-to-one selector. The metastable true random number generator has the advantages of being capable of well counteracting inherent delay deviations, high in automation degree and high in output rate and having an operating point not prone to deviation.

First claim

What is claimed is:

1. A metastable true random number generator realized on an FPGA, characterized in that comprises:
a 1 st decoder;
a 2 nd decoder;
a binary counter;
a D flip-flop;
a delay circuit; and
a postprocessing circuit,
wherein the binary counter is used for outputting a 12-bit digital signal,
wherein the 1 st decoder and the 2 nd decoder are each provided with a 6-bit input terminal and a 32-bit output terminal,
wherein a higher 6-bit digital signal of the 12-bit digital signal output by the binary counter is connected to the 6-bit input terminal of the 1 st decoder, and a lower 6-bit digital signal of the 12-bit digital signal output by the binary counter is connected to the 6-bit input terminal of the 2 nd decoder,
wherein the D flip-flop is provided with an input terminal, a clock terminal and an output terminal,
wherein the delay circuit comprises a configurable delay chain,
wherein the configurable delay chain comprises a rough adjustment circuit and a fine adjustment circuit,
wherein the rough adjustment circuit comprises 32 rough adjustment cells, each rough adjustment cell is provided with an input terminal, a configuration terminal and an output terminal,
wherein the input terminal of the 1 st rough adjustment cell is the input terminal of the rough adjustment circuit, wherein the output terminal of the n th rough adjustment cell is connected to the input terminal of the (n+1) th rough adjustment cell, wherein n=1, 2, . . . , 31, and the output terminal of the 32 nd rough adjustment cell is the output terminal of the rough adjustment circuit, wherein the configuration terminals of the 32 rough adjustment cells form the 32-bit configuration terminal of the rough adjustment circuit,
wherein each rough adjustment cell comprises a 1 st 6-input lookup table and a two-to-one selector,
wherein each 1 st 6-input lookup table is provided with 6 input ports and an output port, wherein each two-to-one selector is provided with a 1 st input terminal, a 2 nd input terminal, a selection terminal and an output terminal,
wherein the 1 st input port of each 1 st 6-input lookup table is connected to the Pt input terminal of the corresponding two-to-one selector and to the input terminal of the corresponding rough adjustment cell, wherein the 2 nd input port, the 3 rd input port, the 4 th input port, the 5 th input port and the 6 th input port of each 1 st 6-input lookup table are all connected to a low level 0,
wherein the output port of each 1 st 6-input lookup table is connected to the 2 nd input terminal of the corresponding two-to-one selector,
wherein the selection terminal of each two-two-one selector is the configuration terminal of the corresponding rough adjustment cell, and the output terminal of each two-to-one selector is the output terminal of the corresponding rough adjustment cell,
wherein the fine adjustment circuit is provided with an input terminal, a 32-bit configuration terminal and an output terminal,
wherein the input terminal of the rough adjustment circuit is connected to the clock terminal of the D flip-flop,
wherein the 32-bit configuration terminal of the rough adjustment circuit is connected to the 32-bit output terminal of the 1 st decoder in a one-to-one corresponding mode, and the output terminals of the rough adjustment cells are connected to the input terminal of the fine adjustment circuit, wherein the output terminal of the fine adjustment circuit is connected to the input terminal of the D flip-flop,
wherein the 32-bit configuration terminal of the fine adjustment circuit is connected to the 32-bit output terminal of the 2 nd decoder in a one-to-one corresponding mode,
wherein the metastable true random number generator further comprises a sampling analysis circuit and a monitoring circuit,
wherein the output terminal of the D flip-flop is connected to an input terminal of the postprocessing circuit and an input terminal of the sampling analysis circuit, wherein an output terminal of the sampling analysis circuit is connected to an input terminal of the monitoring circuit, wherein an output terminal of the monitoring circuit is connected to an input terminal of the binary counter,
wherein the sampling analysis circuit acquires output data of the output terminal of the D flip-flop in real time, every 200 bits of output data acquired are regarded as a set, and the percent of bits equal to 1 in this set of output data is generated as a calculation result; and the calculation result is then sent to the monitoring circuit, and the monitoring circuit generates a control signal according to the calculation result and sends the control signal to the binary counter,
when the percent of bits equal to 1 is over 80%, the monitoring circuit controls the value of the binary counter to plus 3,
when the percent of bits equal to 1 is smaller than 80% and greater than 52%, the monitoring circuit controls the value of the binary counter to plus 1,
when the percent of bits equal to 1 is smaller than 52% and greater than 48%, the monitoring circuit keeps the value of the binary counter unchanged,
when the percent of bits equal to 1 is smaller than 48% and greater than 20%, the monitoring circuit controls the value of the binary counter to minus 1,
when the percent of bits equal to 1 is smaller than 20%, the monitoring control module controls the value of the binary counter to minus 3,
wherein under the control of the monitoring circuit, the binary counter generates and outputs a corresponding 12-bit digital signal,
wherein under the control of the binary counter, the 1 st decoder and the 2 nd decoder generate corresponding decoding signals to configure the rough adjustment circuit and the fine adjustment circuit in real time.

2. The metastable true random number generator realized on the FPGA according to claim 1 , characterized in that the fine adjustment circuit comprises 32 fine adjustment cells, wherein each fine adjustment cell is provided with an input terminal, a configuration terminal and an output terminal,
wherein the input terminal of the 1 st fine adjustment cell is the input terminal of the fine adjustment circuit,
wherein the output terminal of the n th fine adjustment cell is connected to the input terminal of the (n+1) th fine adjustment cell, wherein n=1, 2, 3, . . . 31, and the output terminal of the 32 nd fine adjustment cell is the output terminal of the fine adjustment circuit,
wherein the configuration terminals of the 32 fine adjustment cells form the 32-bit configuration terminal of the fine adjustment circuit.

3. The metastable true random number generator realized on the FPGA according to claim 2 , characterized in that each fine adjustment cell comprises a 2 nd 6-input lookup table, and each 2 nd 6-input lookup table is provided with 6 input ports and an output port,
wherein the 1 st input port of each 2 nd 6-input lookup table is the input terminal of the corresponding fine adjustment cell, and the 2 nd input port, the 3 rd input port, the 4 th input port, the 5 th input port and the 6 th input port of each 2 nd 6-input lookup table are connected to a connecting terminal, and the connecting terminal is the configuration terminal of the corresponding fine adjustment cell,
wherein the output port of each 2 nd 6-input lookup table is the output terminal of the corresponding fine adjustment cell.

Assignees

• Univ Ningbo

Inventors

• Wang Pengjun
• Fang Hongzhen
• Zhang Yuejun

Classifications

• H03K3/84

  Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators · CPC title

• G06F7/588 Primary

  Random number generators, i.e. based on natural stochastic processes · CPC title

• G06F7/58

  Random or pseudo-random number generators · CPC title