High frequency circuit

Patent metadata

Field	Value
Publication number	US-10512153-B2
Application number	US-201616091467-A
Country	US
Kind code	B2
Filing date	Apr 27, 2016
Priority date	Apr 27, 2016
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

A printed wiring board includes conductor layers, a core layer having an opening, and a build-up layer. A high frequency device placed within the opening is installed such that a mirror surface is thermally connected to a conductor layer for heat dissipation facing the opening from a lower surface side of the core layer, and terminals on the terminal surface are electrically connected to conductor layers formed on an upper surface side of the core layer.

First claim

The invention claimed is:

1. A high frequency circuit comprising: a substrate that includes a first dielectric layer having an opening which penetrates the first dielectric layer in a layer thickness direction, second dielectric layers laminated on a lower surface and an upper surface of the first dielectric layer, and a plurality of conductor layers provided in the first dielectric layer and at least one of the second dielectric layers; a first high frequency device that is placed within the opening, the first high frequency device being installed such that a device back surface opposite a terminal surface is thermally and closely connected to a conductor layer for heat dissipation out of the plurality of conductor layers, the conductor layer for heat dissipation provided at a lower surface side of the first dielectric layer, and terminals on the terminal surface are electrically connected to terminal conductor layers out of the plurality of conductor layers through a first via hole provided in the at least one of the second dielectric layers, the terminal conductor layers being formed on an upper surface side of the first dielectric layer; and a second high frequency device that is installed such that a terminal surface thereof faces a surface layer of the upper surface side of the first dielectric layer in the substrate and that the terminals on the terminal surface are electrically connected to the terminal conductor layers, wherein the first and second high frequency devices are disposed at different positions in a planar direction on the substrate, and wherein signal terminals of the first and second high frequency devices are separated by a ground terminal.

2. The high frequency circuit according to claim 1 , wherein the second high frequency device is molded with resin.

3. The high frequency circuit according to claim 2 , wherein the second high frequency device includes a device back surface installed opposite a terminal surface and exposed from the resin.

4. The high frequency circuit according to claim 2 , wherein the second high frequency device includes a device back surface;
the circuit further comprising a metal plate thermally connected to the device back surface opposite the terminal surface of the second high frequency device, wherein the metal plate is exposed from the resin.

5. The high frequency circuit according to claim 3 , further comprising a first shield that covers the device back surface of the second high frequency device and the resin, and that is electrically connected to a conductor layer having a ground potential.

6. The high frequency circuit according to claim 1 , wherein the terminal surface of the first high frequency device and the terminal surface of the second high frequency device have ground terminals arranged around a signal terminal at intervals that are designed to reduce leakage of a high frequency signal in a usable frequency band.

7. The high frequency circuit according to claim 4 , further comprising a second shield that covers the resin and the metal plate exposed from the resin and that is electrically connected to a conductor layer having a ground potential.

8. The high frequency circuit according to claim 1 , wherein the second high frequency device has a device back surface and is installed such that
a conductor layer having a ground potential is provided on the device back surface opposite the terminal surface, and
a ground terminal on the terminal surface is electrically connected through a second via hole to the conductor layer formed on the device back surface, the second via hole penetrating the second high frequency device in a thickness direction.

9. The high frequency circuitry according to claim 1 , further comprising a metal cap that covers a surface of the substrate, on which the second high frequency device is installed, and that is electrically connected to a conductor layer having a ground potential and being formed on the substrate.

10. The high frequency circuit according to claim 1 , wherein the first dielectric layer has an upper surface side; the second dielectric layers are laminated with two or more dielectric layers onto the upper surface side of the first dielectric layer, at least one of the signal terminals of the first high frequency device is electrically connected to the conductor layers for propagating a signal in the at least one of the second dielectric layers, and the conductor layers are surrounded by a ground potential provided around the conductor layers for signal propagation.

11. The high frequency circuit according to claim 10 , wherein the at least one of the second dielectric layers is laminated on the lower surface of the first dielectric layer with a same number of layers as on the upper surface thereof.

Assignees

• Mitsubishi Electric Corp

Inventors

• Ishibashi Hidenori
• Ishida Kiyoshi
• Kuwata Eigo
• Tarui Yukinobu
• Yoshioka Hideharu
• Aoyama Hiroyuki
• Tsuru Masaomi

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title