Thin film transistor and fabrication method thereof, array substrate and display device

Patent metadata

Field	Value
Publication number	US-10510901-B2
Application number	US-201515127262-A
Country	US
Kind code	B2
Filing date	Sep 24, 2015
Priority date	Jun 24, 2015
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

A thin film transistor and a fabrication method thereof, an array substrate and a display device are provided. The thin film transistor comprises a gate electrode, an active layer, a source electrode and a drain electrode. The source electrode and the drain electrode include a first conductive layer provided on the active layer, and an etching rate of a material of the first conductive layer is greater than an etching rate of a material of the active layer in an etching liquid. The problem that the active layer of the thin film transistor is easily corroded in a back channel etch process is avoided, a number of patterning processes is reduced, and fabrication cost is reduced.

First claim

The invention claimed is:

1. A thin film transistor, comprising a gate electrode, an active layer, a source electrode, and a drain electrode, wherein,
the source electrode and the drain electrode each include a first conductive layer and a second conductive layer;
the first conductive layer is provided on the active layer and directly contacts the active layer;
in an etching liquid, an etching rate of a material of the first conductive layer is greater than an etching rate of a material of the active layer;
the second conductive layer is provided on a side, facing away from the active layer, of the first conductive layer and does not directly contact the active layer, wherein a conductivity of the second conductive layer is greater than a conductivity of the first conductive layer; and
the material of the first conductive layer comprises one or more of oxygen-doped zinc nitride, silicon-doped zinc oxide, germanium-doped zinc oxide, titanium-doped zinc oxide, hafnium-doped zinc oxide, yttrium-doped zinc oxide, zirconium-doped zinc oxide, and indium-doped cadmium oxide.

2. The thin film transistor according to claim 1 , wherein,
the material of the active layer includes an oxide semiconductor; and
the etching liquid includes an acidic solution or an alkaline solution.

3. The thin film transistor according to claim 2 , wherein, the material of the active layer includes indium gallium zinc oxide; and the etching liquid includes hydrochloric acid, formic acid, acetic acid or tetramethyl ammonium hydroxide.

4. The thin film transistor according to claim 1 , wherein, the material of the active layer includes an oxide semiconductor.

5. The thin film transistor according to claim 1 , wherein, the etching liquid includes an acidic solution or an alkaline solution.

6. The thin film transistor according to claim 1 , wherein, a material of the second conductive layer includes one or more of molybdenum, aluminum, titanium, and copper.

7. The thin film transistor according to claim 1 , wherein, an insulating layer is not provided between the first conductive layer and the active layer along a direction perpendicular to a plane where the active layer is located.

8. An array substrate, comprising the thin film transistor according to claim 1 .

9. A display device, comprising the array substrate according to claim 8 .

10. A fabrication method of a thin film transistor, comprising:
providing a base substrate, forming a gate metal film on the base substrate, and forming a pattern including a gate electrode by a patterning process; and
forming a gate insulating layer, an active film, and a source electrode and drain electrode film on the base substrate, and forming a pattern including an active layer, a source electrode, and a drain electrode by a patterning process,
wherein, the source electrode and drain electrode film includes a first conductive film and a second conductive film,
the first conductive film is provided on the active film and directly contacts the active film,
in an etching liquid, an etching rate of a material of the first conductive film is greater than an etching rate of a material of the active film,
the second conductive film is formed on a side, facing away from the active film, of the first conductive film and does not directly contact the active film, wherein a conductivity of the second conductive film is greater than a conductivity of the first conductive film, and
the material of the first conductive film includes one or more of oxygen-doped zinc nitride, silicon-doped zinc oxide, germanium-doped zinc oxide, titanium-doped zinc oxide, hafnium-doped zinc oxide, yttrium-doped zinc oxide, zirconium-doped zinc oxide, and indium-doped cadmium oxide.

11. The fabrication method of the thin film transistor according to claim 10 , wherein,
the material of the active film includes an oxide semiconductor; and
the etching liquid includes an acidic solution or an alkaline solution.

12. The fabrication method of the thin film transistor according to claim 10 , wherein, a material of the second conductive film includes one or more of molybdenum, aluminum, titanium, and copper.

13. The fabrication method of the thin film transistor according to claim 10 , wherein,
the active film is patterned with a normal mask by a first patterning process, to form a pattern including the active layer; and
the source electrode and drain electrode film is patterned with another normal mask by a second patterning process, to form a pattern including the source electrode and the drain electrode.

14. The fabrication method of the thin film transistor according to claim 10 , wherein,
the source electrode and drain electrode film is coated with a layer of photoresist;
exposure and development are performed on the photoresist with a dual-tone mask or a gray-tone mask to form a photoresist totally-removed region, a photoresist totally-reserved region, and a photoresist partially-reserved region, wherein the photoresist partially-reserved region corresponds to a region where a gap between the source electrode and the drain electrode is located, the photoresist totally-reserved region corresponds to a region where the pattern of the active layer except for the gap is located, and the photoresist totally-removed region corresponds to a region except for the active layer, and wherein after the development, a thickness of the photoresist in the photoresist totally-reserved region does not change, the photoresist in the photoresist totally-removed region is totally removed, and a thickness of the photoresist in the photoresist partially-reserved region is reduced;
the source electrode and drain electrode film and the active film in the photoresist totally-removed region are totally etched away by a first etching process, to form a pattern including the active layer;
the photoresist in the photoresist partially-reserved region is removed by an ashing process so as to expose the source electrode and drain electrode film in the photoresist partially-reserved region;
the second conductive film of the source electrode and drain electrode film in the photoresist partially-reserved region is totally etched away by a second etching process;
the first conductive film of the source electrode and drain electrode film in the photoresist partially-reserved region is totally etched away by a third etching process, to form a pattern including the source electrode and the drain electrode; and
a remaining portion of the photoresist is stripped off.

15. The fabrication method of the thin film transistor according to claim 14 , wherein, a dry etching is adopted for the second etching process; and wet etching is adopted for the third etching process.

16. The fabrication method of the thin film transistor according to claim 10 , wherein,
the gate insulating layer and the active film are sequentially deposited on the base substrate by using a plasma enhanced chemical vapor deposition method, and the source electrode and drain electrode film is deposited by using a magnetron sputtering method or an evaporation method.

17. A fabrication method of a thin film transistor, comprising:
providing a base substrate, forming a gate metal film on the base substrate, and forming a pattern including a gate electrode by a patterning process; and
forming a gate insulating layer, an active film, and a source electrode and drain electrode film on the base substrate, and forming a pattern including an active layer, a source electrode, and a drain electrode by a patterning process, wherein,
the source electrode and drain e

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Longyan
• Li Yongqian
• Gai Cuili
• Li Quanhu
• Zhang Baoxia
• Yin Jingwen
• Cao Kun
• Wu Zhongyuan
• Wang Gang

Classifications

• H01L27/3262

  Electricity · mapped topic

• H01L27/1225

  Electricity · mapped topic

• H01L27/127

  Electricity · mapped topic

• H01L29/41733

  Electricity · mapped topic

• H01L29/66969

  Electricity · mapped topic