Hard mask removal method

Patent metadata

Field	Value
Publication number	US-10510552-B2
Application number	US-201815957998-A
Country	US
Kind code	B2
Filing date	Apr 20, 2018
Priority date	Aug 5, 2013
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

First claim

It is claimed:

1. A method of removing a hard mask, the method comprising:
patterning gate stacks on a substrate, wherein the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer, wherein the gate stacks are patterned in an isolated region and a dense region, and wherein gate stacks of the isolated region have lower thicknesses than gate stacks of the dense region;
depositing a dielectric layer directly on exposed portions of the substrate between the gate stacks and on the gate stacks, wherein after the dielectric layer is deposited the dielectric layer has a first thickness in the isolated region and a second thickness in the dense region, the first thickness is greater than the second thickness, the first thickness is between a first surface of the dielectric layer that is closest to the substrate in the isolated region and a second surface of the dielectric layer that is farthest from the substrate in the isolated region, the second thickness is between a third surface of the dielectric layer that is closest to the substrate in the dense region and a fourth surface of the dielectric layer that is farthest from the substrate in the dense region, and the first surface of the dielectric layer is level with the third surface of the dielectric layer;
planarizing a first portion of the dielectric layer by a first chemical mechanical polishing (CMP) process, wherein after the first CMP process a difference in the first thickness and the second thickness has been reduced; and
removing the hard mask and a second portion of the dielectric layer by a second CMP process, wherein a thickness difference between the gate stacks in the isolated region and the gate stacks in the dense region is less than 30 Å after the removing of the hard mask and the second portion.

2. The method of claim 1 , wherein during removing the hard mask and the second portion of the dielectric layer, the polysilicon layer of the gate stacks in the dense region is polished for a greater amount of time as compared to the polysilicon layer of the gate stacks in the isolated region.

3. The method of claim 1 , wherein before the dielectric layer is deposited the polysilicon layer of the gate stacks of the isolated region is thinner than the polysilicon layer of the gate stacks of the dense region, and wherein before the dielectric layer is deposited the hard mask of the gate stacks of the isolated region is thinner than the hard mask of the gate stacks of the dense region.

4. The method of claim 1 , wherein each gate stack of the isolated region has smaller pattern features in a dimension of a lateral line width than does each gate stack of the dense region.

5. The method of claim 1 , wherein the depositing is executed using a flowable chemical vapor deposition (FCVD).

6. The method of claim 1 , wherein the hard mask is removed without performing lithography and is removed without performing an etch procedure.

7. The method of claim 1 , wherein the first CMP process and the second CMP process are continuously performed, and the first CMP process and the second CMP process remove material in the dense region and material in the isolated region at a same rate or an approximately same rate as one another.

8. The method of claim 1 , further comprising:
after removing the hard mask and the second portion of the dielectric layer, removing a remaining portion of the dielectric layer using an etch procedure.

9. The method of claim 1 , wherein after the dielectric layer is deposited a difference between the first thickness and the second thickness is up to 1000 Å.

10. The method of claim 1 , wherein planarizing the first portion of the dielectric layer by the first CMP process causes the hard mask of gate stacks in the dense region to be exposed.

11. The method of claim 10 , wherein planarizing the first portion of the dielectric layer by the first CMP process leaves the second portion of the dielectric layer over the hard mask of gate stacks in the isolated region.

12. A method of removing a hard mask, the method comprising:
patterning gate stacks on a substrate, wherein the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer, and wherein the gate stacks are patterned in a dense region and in an isolated region;
depositing a dielectric layer directly on exposed portions of the substrate between the gate stacks and on the gate stacks using a flowable chemical vapor deposition (FCVD) process, wherein the deposited dielectric layer has a higher loading in the isolated region;
planarizing a first portion of the dielectric layer by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer;
removing the hard mask and a second portion of the dielectric layer by the CMP, wherein following the removing of the hard mask and the second portion of the dielectric layer, a third portion of the dielectric layer having a thickness within a range of approximately 150 Å to 1000 Å remains on the substrate; and
removing the third portion of the dielectric layer to expose the substrate between the gate stacks.

13. The method of claim 12 , wherein the third portion of the dielectric layer is removed using an etch procedure.

14. A method of removing a hard mask, the method comprising:
patterning gate stacks on a substrate, wherein the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer, wherein the gate stacks are patterned in a first region and a second region, at least two of the gate stacks are in the first region and at least two of the gate stacks are in the second region, and wherein the at least two of the gate stacks in the second region have lower thicknesses than the at least two of the gate stacks in the first region;
depositing a dielectric layer directly on exposed portions of the substrate between the gate stacks and on the gate stacks, wherein after the dielectric layer is deposited a first surface of the dielectric layer overlies the first region and is farthest from the substrate in the first region, a second surface of the dielectric layer overlies the second region and is farthest from the substrate in the second region, and the second surface of the dielectric layer is farther from the substrate that the first surface of the dielectric layer;
planarizing a first portion of the dielectric layer by chemical mechanical polishing (CMP) to completely remove the dielectric layer over the at least two of the gate stacks in the first region and to partially remove the dielectric layer over the at least two of the gate stacks in the second region; and
removing the hard mask over the at least two of the gate stacks in the first region the at least two of the gate stacks in the second region and a second portion of the dielectric layer over the at least two of the gate stacks in the second region by the CMP.

15. The method of claim 14 , wherein, prior to the planarizing, the polysilicon layer of the at least two of the gate stacks in the second region is thinner than the polysilicon layer of the at least two of the gate stacks in the first region, and wherein the hard mask of the at least two of the gate stacks in the second region is thinner than the hard mask of the at least two of the gate stacks in the first region.

16. The method of claim 14 , wherein each gate stack of the at least two of the gate stacks in the second region has smaller pattern features in a dimension of a lateral linewidth than does each gate stack of the at least two of the gate stacks in the first region.

17. Th

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Manfacturing Company Ltd

Inventors

• Tu Che-Hao
• Hong William Weilun
• Chen Ying-Tsung

Classifications

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10D64/01326

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title

• H10P52/402

  of semiconductor materials · CPC title

• H10P95/062 Primary

  involving a dielectric removal step · CPC title

• H01L21/823437

  Electricity · mapped topic