Multilayer ceramic capacitor and method for making multilayer ceramic capacitor

US10510496B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10510496-B2
Application numberUS-201816158331-A
CountryUS
Kind codeB2
Filing dateOct 12, 2018
Priority dateJul 16, 2015
Publication dateDec 17, 2019
Grant dateDec 17, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A multilayer ceramic capacitor includes a multilayer body that includes ceramic layers and inner conductor layers arranged in a stacking direction and that includes a first surface in which the inner conductor layers are exposed, and an outer electrode on the first surface of the multilayer body. The inner conductor layers contain Ni. The outer electrode includes a base layer that directly covers at least a portion of the first surface and is connected to the inner conductor layers. The base layer contains a metal and glass and includes a Ni diffusion portion connected to the inner conductor layers, the Ni diffusion portion containing Ni. A ratio of a diffusion depth of the Ni diffusion portion to a thickness of the base layer is smaller on two of the inner conductor layers that are located outermost than on other inner conductor layers.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for making a multilayer ceramic capacitor, the method comprising: a step of applying a conductive paste containing Cu powder to a first surface of a multilayer body that includes a plurality of ceramic layers and a plurality of inner conductor layers arranged in a stacking direction, the inner conductor layers being exposed at the first surface; and a step of baking the conductive paste on the first surface; wherein the Cu powder has an average particle diameter of about 0.5 μm or more and about 2.0 μm or less; and in the step of baking the conductive paste, water is added to a baking atmosphere while a peak temperature is maintained. 2. The method for making a multilayer ceramic capacitor according to claim 1 , wherein, in the step of baking the conductive paste, water is added in a later stage of a period during which the peak temperature is maintained. 3. The method for making a multilayer ceramic capacitor according to claim 1 , wherein the conductive paste further contains glass, and the average particle diameter of the Cu powder is smaller than an average particle diameter of the glass.

Assignees

Inventors

Classifications

  • Stacked capacitors (H01G4/33 takes precedence) · CPC title

  • Fried electrodes · CPC title

  • H01G13/006Primary

    Apparatus or processes for applying terminals · CPC title

  • Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

  • characterised by the material of the terminals · CPC title

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What does patent US10510496B2 cover?
A multilayer ceramic capacitor includes a multilayer body that includes ceramic layers and inner conductor layers arranged in a stacking direction and that includes a first surface in which the inner conductor layers are exposed, and an outer electrode on the first surface of the multilayer body. The inner conductor layers contain Ni. The outer electrode includes a base layer that directly cove…
Who is the assignee on this patent?
Murata Manufacturing Co
What technology area does this patent fall under?
Primary CPC classification H01G13/006. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 17 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).