Integrated circuit devices configured to control discharge of a control gate voltage

Patent metadata

Field	Value
Publication number	US-10510397-B2
Application number	US-201916430896-A
Country	US
Kind code	B2
Filing date	Jun 4, 2019
Priority date	Dec 28, 2017
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

Integrated circuit devices include a first node, a second node, a transistor connected between the first node and the second node, a current path between a control gate of the transistor and the second node, and a controller configured to concurrently discharge a voltage level of the first node and a voltage level of the second node, monitor a representation of a voltage difference between the voltage level of the first node and a voltage level of the control gate of the transistor while discharging the voltage level of the first node and discharging the voltage level of the second node, activate the current path if the voltage difference is deemed to be greater than a first value, and deactivate the current path if the voltage difference is deemed to be less than a second value.

First claim

What is claimed is:

1. An integrated circuit device, comprising:
a first node;
a second node;
a transistor connected between the first node and the second node;
a current path between a control gate of the transistor and the second node; and
a controller, wherein the controller is configured to:
concurrently discharge a voltage level of the first node and a voltage level of the second node;
monitor a representation of a voltage difference between the voltage level of the first node and a voltage level of the control gate of the transistor while discharging the voltage level of the first node and discharging the voltage level of the second node;
activate the current path if the voltage difference is deemed to be greater than a first value; and
deactivate the current path if the voltage difference is deemed to be less than a second value.

2. The integrated circuit device of claim 1 , wherein the controller being configured to monitor the representation of the voltage difference between the voltage level of the first node and the voltage level of the control gate of the transistor comprises the controller being configured to:
monitor an output of a first comparator having a first input capacitively coupled to the first node and a second input capacitively coupled to the control gate of the transistor, wherein the output of the first comparator is configured to indicate whether the voltage difference is deemed to be greater than the first value; and
monitor an output of a second comparator having a first input capacitively coupled to the control gate of the transistor and a second input capacitively coupled to the first node, wherein the output of the second comparator is configured to indicate whether the voltage difference is deemed to be less than the second value.

3. The integrated circuit device of claim 1 , wherein the controller, after activating the current path if the voltage difference is deemed to be greater than the first value, is further configured to:
maintain activation of the current path if the voltage difference is no longer deemed to be greater than the first value and the voltage difference is deemed to be greater than the second value.

4. The integrated circuit device of claim 3 , wherein the controller, after deactivating the current path if the voltage difference is deemed to be less than the second value, is further configured to:
maintain deactivation of the current path if the voltage difference is no longer deemed to be less than the second value and the voltage difference is deemed to be less than the first value.

5. The integrated circuit device of claim 1 , wherein the first value is selected such that the controller is configured to activate the current path before the voltage difference is deemed to be greater than a breakdown voltage of the transistor, and wherein the second value is selected such that the controller is configured to deactivate the current path before the voltage difference is deemed to be less than a threshold voltage of the transistor.

6. The integrated circuit device of claim 1 , wherein the transistor is a first transistor, and wherein the current path comprises:
a second transistor connected between the second node and the control gate of the first transistor; and
a third transistor connected between the second transistor and the control gate of the first transistor;
wherein a control gate of the third transistor is connected to the control gate of the first transistor;
wherein the controller is configured to activate the current path by activating the second transistor; and
wherein the controller is configured to deactivate the current path by deactivating the second transistor.

7. An integrated circuit device, comprising:
a first node;
a second node selectively connected to the first node through a transistor;
a first voltage node capacitively coupled to a voltage level of the first node;
a second voltage node capacitively coupled to the voltage level of the first node;
a third voltage node capacitively coupled to a voltage level of a control gate of the transistor;
a fourth voltage node capacitively coupled to the voltage level of the control gate of the transistor;
a current path between the second node and the control gate of the transistor; and
a controller configured to:
apply a first voltage level to the first voltage node, then allow the first voltage node to electrically float;
apply a second voltage level, lower than the first voltage level, to the second voltage node, then allow the second voltage node to electrically float;
concurrently discharge the voltage level of the first node and a voltage level of the second node;
compare a voltage level of the first voltage node to a voltage level of the third voltage node;
compare a voltage level of the second voltage node to a voltage level of the fourth voltage node;
activate the current path while the voltage level of the third voltage node is deemed to be greater than the voltage level of the first voltage node; and
deactivate the current path while the voltage level of the fourth voltage node is deemed to be less than the voltage level of the second voltage node.

8. The integrated circuit device of claim 7 , wherein the controller is configured to apply the second voltage level to the second voltage and to apply the first voltage level to the first voltage node concurrently.

9. The integrated circuit device of claim 7 , wherein the controller being configured to discharge the voltage level of the first node comprises the controller being configured to discharge the voltage level of the first node to the second node through the transistor.

10. The integrated circuit device of claim 7 , wherein the controller is further configured to:
electrically float the first voltage node and electrically float the third voltage node while comparing the voltage level of the first voltage node to the voltage level of a third voltage node; and
electrically float the second voltage node and electrically float the fourth voltage node while comparing the voltage level of the second voltage node to the voltage level of the fourth voltage node.

11. The integrated circuit device of claim 10 , wherein the controller is further configured to:
adjust a level of charge on the third voltage node prior to applying the first voltage level to the first voltage node, and prior to electrically floating the third voltage node; and
adjust a level of charge on the fourth voltage node prior to applying the second voltage level to the second voltage node, and prior to electrically floating the fourth voltage node.

12. The integrated circuit device of claim 7 , wherein the transistor is a first transistor, and wherein the current path comprises:
a second transistor between the second node and the control gate of the transistor;
wherein activating the current path comprises activating the second transistor; and
wherein deactivating the current path comprises deactivating the second transistor.

13. The integrated circuit device of claim 7 , wherein the first voltage level is selected such that the voltage level of the third voltage node would be deemed to be greater than the voltage level of the first voltage node before a voltage difference between the voltage level of the control gate of the transistor and the voltage level of the first node exceeds a breakdown voltage of the transistor, and wherein the second voltage level is selected such that the voltage level of the fourth voltage node would be deemed to be less than the voltage level of the second voltage node before a voltage difference between the voltage level of the c

Assignees

• Micron Technology Inc

Inventors

• Yamada Shigekazu

Classifications

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C7/1048 Primary

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C16/28

  using differential sensing or reference cells, e.g. dummy cells · CPC title