Control circuit, control method and display apparatus

Patent metadata

Field	Value
Publication number	US-10510316-B2
Application number	US-201816128794-A
Country	US
Kind code	B2
Filing date	Sep 12, 2018
Priority date	Oct 31, 2017
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

The present disclosure provides a control circuit, a control method, and a display apparatus. The control sub-circuit is connected to a first voltage input terminal, a second voltage input terminal and the driving sub-circuit, and configured to boost a second voltage input from the second voltage input terminal to obtain a third voltage when it is detected that a first voltage input from the first voltage input terminal is lower than or equal to a first reference voltage, and output the third voltage to the driving sub-circuit; the driving sub-circuit is connected to the control sub-circuit, a fourth voltage input terminal and scan lines of a display panel, and configured to output the third voltage to the scan lines when it is detected that a fourth voltage input from the fourth voltage input terminal is lower than or equal to a second reference voltage.

First claim

We claim:

1. A control circuit comprising:
a control sub-circuit connected to a first voltage input terminal, a second voltage input terminal and the driving sub-circuit, and configured to boost a second voltage input from the second voltage input terminal to obtain a third voltage when it is detected that a first voltage input from the first voltage input terminal is lower than or equal to a first reference voltage, and output the third voltage to the driving sub-circuit; and
a driving sub-circuit connected to the control sub-circuit, a fourth voltage input terminal and scan lines of a display panel, and configured to output the third voltage to the scan lines when it is detected that a fourth voltage input from the fourth voltage input terminal is lower than or equal to a second reference voltage.

2. The control circuit of claim 1 , wherein the control sub-circuit comprises a first comparison circuit, a first output circuit, and a boost control circuit;
the first comparison circuit is connected to the first voltage input terminal, the first output circuit and the boost control circuit, and configured to compare the first voltage and the first reference voltage, and output, according to a comparison result, a first enabling signal to the first output circuit and the boost control circuit respectively;
the first output circuit is connected to the second voltage input terminal, the first comparison circuit and the driving sub-circuit, and configured to output the second voltage to the driving sub-circuit when the first enabling signal meets a first preset condition;
the boost control circuit is connected to the second voltage input terminal, the first comparing circuit and the driving sub-circuit, and configured to boost the second voltage to the third voltage and output the third voltage to the driving sub-circuit when the first enabling signal meets a second preset condition.

3. The control circuit of claim 2 , wherein the first output circuit comprises an inverter and a first transistor, the first transistor comprises a first control electrode, a first electrode and a second electrode;
the inverter is connected to the first comparison circuit and the first control electrode, and configured to output a signal having a phase opposite to that of the first enabling signal to the first control electrode according to the first enabling signal;
the first electrode of the first transistor is connected to the second voltage input terminal, and the second electrode of the first transistor is connected to the driving sub-circuit; the first transistor is configured to output, by the second electrode, the second voltage to the driving sub-circuit when the signal output by the inverter to the first control electrode turns on the first transistor.

4. The control circuit of claim 3 , wherein the boost control circuit comprises a second transistor and a boost circuit;
the second transistor comprises a second control electrode, a third electrode and a fourth electrode; the second control electrode is connected to the first comparison circuit, the third electrode is connected to the second voltage input terminal, and the fourth electrode is connected to the boost circuit;
the boost circuit is connected to the fourth electrode and the driving sub-circuit, and configured to boost the second voltage to the third voltage and output the third voltage to the driving sub-circuit when the first enabling signal turns on the second transistor;
wherein the second transistor has the same channel type as the first transistor.

5. The control circuit of claim 4 , wherein the first comparison circuit comprises a first voltage comparator, an inverted terminal of the first voltage comparator is connected to the first voltage input terminal, and an in-phase terminal of the first voltage comparator is connected to the first reference voltage;
the first output circuit is configured to output the second voltage to the driving sub-circuit when the first voltage is higher than the first reference voltage and the first enabling signal is a low level signal;
the boost control circuit is configured to boost the second voltage to the third voltage and output the third voltage to the driving sub-circuit when the first voltage is lower than or equal to the first reference voltage and the first enabling signal is a high level signal.

6. The control circuit of claim 5 , wherein the first transistor and the second transistor are N-type transistors.

7. The control circuit of claim 1 , wherein the driving sub-circuit comprises a second comparison circuit and a gate driving circuit;
the second comparison circuit is connected to the fourth voltage input terminal and the gate driving circuit, and configured to compare the fourth voltage and the second reference voltage, and output, according to a comparison result, a second enabling signal to the gate driving circuit;
the gate driving circuit is connected to the control sub-circuit, the second comparison circuit and the scan lines of the display panel, and configured to output the third voltage to the scan lines when the second enabling signal meets a third preset condition.

8. The control circuit of claim 7 , wherein the second comparison circuit comprises a second voltage comparator, an in-phase terminal of the second voltage comparator is connected to the fourth voltage input terminal, and an inverted terminal of the second voltage comparator is connected to the second reference voltage;
the gate driving circuit is configured to output the third voltage to the scan lines when the fourth voltage is lower than or equal to the second reference voltage and the second enabling signal is a low level signal.

9. The control circuit of claim 8 , wherein the fourth voltage is a voltage that is obtained by processing the first voltage by a power manager of the display panel and provided to digital circuitry of the display panel.

10. The control circuit of claim 9 , wherein the first reference voltage and the second reference voltage are set so that the first voltage is lower than or equal to the first reference voltage when the fourth voltage is lower than or equal to the second reference voltage.

11. A display apparatus comprising the control circuit of claim 1 .

12. A control method applied to a control circuit comprising a control sub-circuit and a driving sub-circuit, wherein the control sub-circuit is connected to a first voltage input terminal, a second voltage input terminal and the driving sub-circuit, and the driving sub-circuit is connected to the control sub-circuit, a fourth voltage input terminal and scan lines of a display panel; the control method comprising:
boosting a second voltage input from a second voltage input terminal to obtain a third voltage when a control sub-circuit detects that a first voltage input from a first voltage input terminal is lower than or equal to a first reference voltage, and outputting the third voltage to a driving sub-circuit;
outputting the third voltage to scan lines of the display panel when the driving sub-circuit detects that a fourth voltage input from a fourth voltage input terminal is lower than or equal to a second reference voltage.

13. The control method of claim 12 , wherein when the control sub-circuit detects that the first voltage is greater than the first reference voltage, a second voltage is output to the driving sub-circuit.

14. The control method of claim 12 , wherein the fourth voltage is a voltage that is obtained by processing the first voltage by a power manager of the display panel and provided to digital circuitry of the display panel.

15. The con

Assignees

• Boe Technology Group Co Ltd
• Chongqing Boe Optoelectronics Tech Co Ltd

Inventors

• Xiong Lijun
• Tang Xiuzhu
• Zhang Zhi
• Chen Shuai
• Dong Xing
• Tang Taoliang
• Zhao Jingpeng
• Tian Zhenguo
• Liang Xuebo
• Hu Shuang

Classifications

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G2330/027

  Arrangements or methods related to powering off a display · CPC title

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• H03K5/2472

  using field effect transistors (H03K5/2436 takes precedence) · CPC title

• G09G2320/0257

  Reduction of after-image effects · CPC title