Transferring data between memory system and buffer of a master device

Patent metadata

Field	Value
Publication number	US-10509743-B2
Application number	US-201715612072-A
Country	US
Kind code	B2
Filing date	Jun 2, 2017
Priority date	Jun 20, 2016
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

A master device has a buffer for storing data transferred from, or to be transferred to, a memory system. Control circuitry issues from time to time a group of one or more transactions to request transfer of a block of data between the memory system and the buffer. Hardware or software mechanism can be provided to detect at least one memory load parameter indicating how heavily loaded the memory system is, and a group size of the block of data transferred per group can be varied based on the memory load parameter. By adapting the size of the block of data transferred per group based on memory system load, a better balance between energy efficiency and quality of service can be achieved.

First claim

We claim:

1. A master device comprising:
a buffer to store data transferred from a memory system or data to be transferred to the memory system; and
control circuitry to issue, when there is sufficient space in the buffer to store a block of data of size equal to a group size, a group of one or more transactions to request transfer of a block of data having said group size between the memory system and the buffer;
wherein the control circuitry is configured to detect at least one memory load parameter indicative of how heavily loaded the memory system is, and to vary said group size in dependence on said at least one memory load parameter;
wherein the control circuitry is configured to detect whether the at least one memory load parameter indicates one of a first load condition, a second load condition in which the memory system is more heavily loaded than the first load condition, and a third load condition in which the memory system is more heavily loaded than the second load condition; and
when varying the group size in dependence on the at least one memory load parameter, the control circuitry is configured to:
select a smaller group size when detecting the second load condition than when detecting the first load condition, and
select a smaller group size when detecting the second load condition than when detecting the third load condition.

2. The master device according to claim 1 , wherein the control circuitry is configured to detect a predetermined buffer occupancy condition comprising one of:
an underrun condition when a buffer occupancy of the buffer drops to or below an underrun threshold; and
an overrun condition when the buffer occupancy of the buffer rises to or above an overrun threshold.

3. The master device according to claim 2 , wherein in the presence of said predetermined buffer occupancy condition, the control circuitry is configured to set the group size to a predetermined group size; and
when said predetermined buffer occupancy condition is absent, the control circuitry is configured to vary the group size in dependence on the at least one memory load parameter.

4. The master device according to claim 2 , wherein in the presence of said predetermined buffer occupancy condition, the control circuitry is configured to issue transactions specifying an ordering attribute identifying that the transactions specifying said ordering attribute should be serviced by the memory system in the same order that the transactions specifying said ordering attribute are issued by the master device.

5. The master device according to claim 2 , wherein the control circuitry is configured to trigger an exception condition in response to detecting said predetermined buffer occupancy condition.

6. The master device according to claim 1 , wherein the control circuitry is configured to issue a next group of one or more transactions in response to detecting one of:
a buffer occupancy of the buffer reaching or passing beyond a transaction-issuing threshold level; or
data being read out from or written to the buffer which has a relative position within a predetermined structural unit of data equal to a transaction-issuing threshold position.

7. The master device according to claim 6 , wherein when varying the group size in dependence on said at least one memory load parameter, the control circuitry is configured to vary the transaction-issuing threshold level or transaction-issuing threshold position in dependence on said at least one memory load parameter.

8. The master device according to claim 1 , wherein the control circuitry is configured to suppress issuing of further transactions when a maximum number of outstanding transactions issued by the master device are still outstanding; and
the control circuitry is configured to vary said maximum number of outstanding transactions in dependence on said at least one memory load parameter.

9. The master device according to claim 1 , wherein the control circuitry is configured to vary the group size between a minimum allowable group size and a maximum allowable group size.

10. The master device according to claim 9 , wherein at least one of the minimum allowable group size and the maximum allowable group size is programmable by software.

11. The master device according to claim 1 , wherein the control circuitry is configured to vary the group size by varying a size of a portion of data transferred per transaction in the group.

12. The master device according to claim 1 , wherein the control circuitry is configured to vary the group size by varying a number of transactions issued in the group.

13. The master device according to claim 1 , comprising a read buffer to store data transferred from a memory system, and a write buffer to store data to be transferred to the memory system;
wherein the control circuitry is configured to issue within a same group of transactions both read transactions requesting reading of data from the memory system to the read buffer and write transactions requesting writing of data from the write buffer to the memory system.

14. The master device according to claim 1 , wherein the at least one memory load parameter comprises a signal received from the memory system indicative of how heavily loaded the memory system is.

15. The master device according to claim 1 , wherein the at least one memory load parameter comprises a time between issuing a transaction to the memory system and receiving the data from the memory system in response to the transaction.

16. The master device according to claim 1 , wherein the at least one memory load parameter is dependent on a minimum or maximum buffer occupancy of the buffer reached during a predetermined period.

17. The master device according to claim 16 , wherein the control circuitry is configured to vary the group size in dependence on the minimum or maximum buffer occupancy and a margin amount.

18. The master device according to claim 17 , wherein the margin amount is programmable by software.

19. The master device according to claim 17 , wherein the control circuitry is configured to trigger an exception condition in response to the buffer occupancy dropping to or below the margin amount, or in response to an amount of spare buffer capacity dropping to or below the margin amount.

20. The master device according to claim 16 , wherein the control circuitry is configured to trigger an exception condition in response to the buffer occupancy reaching or passing beyond a previous minimum or maximum buffer occupancy.

21. The master device according to claim 1 , wherein the master device is configured to process a stream of data fetched from storage locations in the memory system identified by a sequential series of addresses.

22. The master device according to claim 1 , wherein the master device comprises a display processor to control display of image data on a display device based on the data in the buffer.

23. The master device according to claim 1 , wherein the master device comprises a direct memory access controller to control output of data from the buffer to a memory or a peripheral device.

24. An apparatus comprising:
the master device of claim 1 ; and
said memory system.

25. A method for controlling a master device comprising a buffer for storing data transferred from a memory system or data to be transferred to the memory system, for which data is transferred between the buffer and the memory

Assignees

• Advanced Risc Mach Ltd

Inventors

• Croxford Daren
• Saeed Sharjeel
• Carter Quinn
• Campbell Michael Andrew

Classifications

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/1673 Primary

  using buffers · CPC title

• Y02D10/14

  Cross-Sectional Technologies · mapped topic

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title