Pixel structure and manufacturing method thereof, array substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-10509286-B2
Application number	US-201615518911-A
Country	US
Kind code	B2
Filing date	Oct 9, 2016
Priority date	Jan 26, 2016
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

A manufacturing method of the invention, comprising: successively forming an insulation layer and a photoresist layer on a transparent substrate; performing an exposure and a development on the photoresist layer by a back exposure process, so as to form a trench in the photoresist layer, an open area of the trench proximal to the insulation layer is larger than that of the trench distal to the insulation layer; removing a portion of insulation material in a region of the insulation layer exposed through the trench by an etching process, so as to form a slot in the insulation layer; forming a metal layer on a side of the photoresist layer distal to the insulation layer, a portion of the metal layer is embedded in the slot; removing the photoresist layer and the metal layer thereon by a stripping process, and retaining the portion of the metal layer in the slot.

First claim

The invention claimed is:

1. A manufacturing method of a pixel structure comprising an insulation layer and a metal layer, the manufacturing method comprising steps of:
successively forming the insulation layer and a photoresist layer on a transparent substrate;
performing an exposure and a development on the photoresist layer by a back exposure process, so as to form a trench in the photoresist layer, an open area of the trench proximal to the insulation layer is larger than that of the trench distal to the insulation layer;
removing a portion of insulation material in a region of the insulation layer exposed through the trench by an etching process, so as to form a slot in the insulation layer;
depositing the metal layer on a side of the photoresist layer distal to the insulation layer, a portion of the metal layer is embedded in the slot, and the portion of the metal layer embedded in the slot has a thickness substantially equal to that of the insulation layer;
removing the photoresist layer and the metal layer thereon by a stripping process, and retaining the insulation layer and the portion of the metal layer in the slot of the insulation layer,
wherein during the back exposure process, a semi-transmission mask plate is used for performing the exposure, so that the cross section shape of the trench along the plane perpendicular to the plane of the transparent substrate is a trapezoid, and the trapezoid has two waists of arc lines, the arc lines protrude toward an inside of the trench.

2. The manufacturing method of claim 1 , wherein the photoresist layer is a transparent layer.

3. The manufacturing method of claim 1 , wherein, during the back exposure process, a full-transmission mask plate is used for performing the exposure, so that a cross section shape of the trench along a plane perpendicular to a plane of the transparent substrate is a trapezoid, and the trapezoid has two waists of straight lines.

4. The manufacturing method of claim 3 , wherein the cross section shape of the trench along the plane perpendicular to the plane of the transparent substrate is an isosceles trapezoid, and the isosceles trapezoid has two waists of straight lines.

5. The manufacturing method of claim 1 , wherein the cross section shape of the trench along the plane perpendicular to the plane of the transparent substrate is an isosceles trapezoid, and the isosceles trapezoid has two waists of arc lines.

6. The manufacturing method of claim 1 , wherein, the pixel structure comprises a thin film transistor, the insulation layer is a gate insulation layer of the thin film transistor, the portion of the metal layer embedded in the slot of the insulation layer is a gate layer of the thin film transistor, an active layer and a source and drain layer are further successively provided above the gate insulation layer.

7. The manufacturing method of claim 6 , wherein, an auxiliary gate insulation layer is further provided between the gate insulation layer and the active layer, the auxiliary gate insulation layer is formed of a material that is the same as that of the gate insulation layer and completely covers the gate insulation layer and the gate layer.

8. The manufacturing method of claim 1 , wherein, the pixel structure comprises a thin film transistor, a pixel electrode layer and a passivation layer, the insulation layer is the passivation layer, and the portion of the metal layer embedded in the slot of the insulation layer is the pixel electrode layer.

9. A pixel structure manufactured by the manufacturing method of claim 1 , comprising an insulation layer and a metal layer embedded in a slot of the insulation layer, the portion of the metal layer embedded in the slot of the insulation layer has a thickness substantially equal to that of the insulation layer.

10. The pixel structure of claim 9 , further comprising a thin film transistor, the insulation layer is a gate insulation layer of the thin film transistor, the metal layer embedded in the slot of the insulation layer is a gate layer of the thin film transistor, an active layer and a source and drain layer are further successively provided above the gate insulation layer.

11. The pixel structure of claim 10 , wherein, an auxiliary gate insulation layer is further provided between the gate insulation layer and the active layer, the auxiliary gate insulation layer is formed of a material that is the same as that of the gate insulation layer and completely covers the gate insulation layer and the gate layer.

12. The pixel structure of claim 9 , further comprising a thin film transistor, a pixel electrode layer and a passivation layer, the insulation layer is the passivation layer, and the metal layer embedded in the slot of the insulation layer is the pixel electrode layer.

13. An array substrate, comprising the pixel structure of claim 9 .

14. A display apparatus, comprising the array substrate of claim 13 .

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Wan Yunhai
• Yang Chengshao
• Han Ling
• Song Botao

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• G02F1/1368 Primary

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title