Method for manufacturing semiconductor wafer

Patent metadata

Field	Value
Publication number	US-10508361-B2
Application number	US-201615772884-A
Country	US
Kind code	B2
Filing date	Nov 8, 2016
Priority date	Nov 10, 2015
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

In a first step, protrusions (42) are formed on a surface of an SiC substrate (40), and the SiC substrate (40) is etched. In a second step, the protrusions (42) of the SiC substrate (40) are epitaxially grown through MSE process, and an epitaxial layer (43a) containing threading screw dislocation, which has been largely grown in the vertical (c-axis) direction as a result of MSE process, is at least partially removed. In a third step, MSE process is performed again on the SiC substrate (40) after the second step, to cause epitaxial layers (43) containing no threading screw dislocation to be grown in the horizontal (a-axis) direction to be connected at the molecular level, so that one monocrystalline 4H—SiC semiconductor wafer (45) having a large area is generated throughout an Si-face or a C-face of the SiC substrate (40).

First claim

The invention claimed is:

1. A method for manufacturing a semiconductor wafer, the method comprising:
a first step of forming protrusions on a surface of an SiC substrate and heating the SiC substrate under Si vapor pressure, to etch the SiC substrate;
a second step of arranging a carbon feed member on the protrusion side of the SiC substrate after the first step with an Si melt interposed therebetween, then heating so that the protrusions of the SiC substrate are epitaxially grown to form epitaxial layers through metastable solvent epitaxy process, the epitaxial growth allowing an epitaxial layer containing threading screw dislocation to be more largely grown in a vertical (c-axis) direction as compared with an epitaxial layer containing no threading screw dislocation, and then removing at least a part of the epitaxial layer containing threading screw dislocation; and
a third step of performing metastable solvent epitaxy process again on the SiC substrate after the second step, to cause epitaxial layers containing no threading screw dislocation to be grown in a horizontal (a-axis) direction to be connected at a molecular level, so that at least one monocrystalline 4H—SiC semiconductor wafer having a large area is generated on an Si-face (0001 face) or a C-face (000-1 face) which is a surface of the SiC substrate.

2. The method for manufacturing a semiconductor wafer according to claim 1 , wherein
the SiC substrate has an off-angle of 0° or close to 0°, and
in the metastable solvent epitaxy process performed in the second step and the third step, polycrystalline 3C—SiC is adopted as the carbon feed member, a heating temperature is set to 1600° C. or more and 2000° C. or less, and Si pressure is set to 10 −5 Torr or more.

3. The method for manufacturing a semiconductor wafer according to claim 1 , wherein
in the second step and the third step, epitaxial layers are formed on a C-face (000-1 face) of the SiC substrate through the metastable solvent epitaxy process.

4. The method for manufacturing a semiconductor wafer according to claim 1 , wherein
in the second step and the third step, epitaxial layers are formed on an Si-face (0001 face) of the SiC substrate through the metastable solvent epitaxy process.

5. The method for manufacturing a semiconductor wafer according to claim 1 , wherein
in the first step, the SiC substrate is irradiated with laser to form a plurality of grooves crossing one another, thus forming protrusions on the SiC substrate, and
in the second step, the epitaxial layer containing threading screw dislocation is irradiated with laser, for removal of this epitaxial layer.

6. The method for manufacturing a semiconductor wafer according to claim 5 , wherein
each of the protrusions has a rectangular upper surface,
each of the protrusions has a length of 20 μm to 40 μm in the vertical (c-axis) direction,
one side of the upper surface of each of the protrusions has a length of 50 μm to 100 μm in the horizontal (a-axis) direction, and
the interval at which adjacent ones of the protrusions are formed is 400 μm to 1000 μm.

7. The method for manufacturing a semiconductor wafer according to claim 5 , wherein
in the second step, the length of an epitaxial layer containing threading screw dislocation in the vertical (c-axis) direction is equal to or more than twice the length of an epitaxial layer containing no threading screw dislocation in the vertical (c-axis) direction.

8. The method for manufacturing a semiconductor wafer according to claim 7 , wherein
in the second step,
an epitaxial layer grown from the protrusion containing threading screw dislocation has a length of about 250 μm in the vertical (c-axis) direction, and a length of about 400 μm in the horizontal (a-axis) direction, and
an epitaxial layer grown from the protrusion containing no threading screw dislocation has a length of about 100 μm in the vertical (c-axis) direction, and a length of about 400 μm in the horizontal (a-axis) direction.

9. The method for manufacturing a semiconductor wafer according to claim 1 , wherein
in the third step, the metastable solvent epitaxy process is performed under a condition that enables an epitaxial layer containing no threading screw dislocation to be grown by 4 mm in the horizontal (a-axis) direction.

10. The method for manufacturing a semiconductor wafer according to claim 1 , wherein
the protrusions are formed in such a manner that imaginary lines each connecting the centers of adjacent ones of the protrusions form an equilateral triangle when the SiC substrate is viewed in a direction perpendicular to <1-100> direction and to <11-20> direction.

11. The method for manufacturing a semiconductor wafer according to claim 1 , wherein
in the second step and the third step, the metastable solvent epitaxy process is performed so as to cause the vertices of hexagonal shapes of epitaxial layers to contact each other.

Assignees

• Kwansei Gakuin Educational Found

Inventors

• Kaneko Tadaaki
• Kutsuma Yasunori
• Ashida Koji

Classifications

• H10P14/3466

  Crystal orientation · CPC title

• H10P14/3408

  Silicon carbide · CPC title

• H10P14/2925

  Surface structures · CPC title

• H10P14/2904

  Silicon carbide · CPC title

• H10P14/263

  using melted materials · CPC title