Scalable fabrication techniques and circuit packaging devices

Patent metadata

Field	Value
Publication number	US-10506715-B2
Application number	US-201415105350-A
Country	US
Kind code	B2
Filing date	Dec 19, 2014
Priority date	Dec 19, 2013
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

Disclosed are highly scalable fabrication methods for producing electronic circuits, devices, and systems. In one aspect, a fabrication method includes attaching an electronic component at a location on a substrate including a flexible and electrically insulative material; forming a template to encase the electronic component by depositing a material in a phase to conform on the surfaces of the electronic component and the substrate, and causing the material to change to solid form; and producing a circuit or electronic device by forming openings in the substrate to expose conductive portions of the electronic component, creating electrical interconnections coupled to at least some of the conductive portions in a selected arrangement on the substrate, and depositing a layer of an electrically insulative and flexible material over the electrical interconnections on the substrate to form a flexible base of the circuit, in which the produced circuit or electronic device is encased.

First claim

What is claimed is:

1. An electronic device packaging, comprising:
a substrate formed from a material that is both flexible and electrically insulative, wherein the substrate includes a side on which one or more electronic components can adhere wherein the substrate includes openings spanning from the side into an interior region of the substrate, and wherein the openings are arranged to align to locations where conductive contacts of the one or more electronic components are designed to be positioned;
interconnection wires including an electrically conductive material, the interconnection wires disposed in the openings and the interior region of the substrate in a particular arrangement based on an electronic device design to electrically connect the one or more electronic components, wherein an interconnection portion of the interconnection wires are configured in a planar layer in the interior region;
a second layer of additional interconnection wires disposed in the interior region of the substrate and electrically coupled to at least some of the interconnection wires, wherein an additional interconnection portion of the additional interconnection wires are configured in a second planar layer in the interior region; and
a circuit element disposed in the interior region of the substrate at the planar layer or the second planar layer and in electrical connection with at least one interconnection wire of the interconnection wires, the circuit element including one or more of a resistor, capacitor, inductor, antenna, or transmission line,
wherein the substrate is structured to have a thickness less than 35 μm.

2. The electronic device packaging as in claim 1 , wherein the one or more electronic components to adhere to the substrate include a second circuit element, a circuit, or a microchip.

3. The electronic device packaging as in claim 2 , wherein, when the one or more electronic components includes the circuit, the circuit includes an integrated circuit, a thin film circuit, a sensor circuit, a transducer circuit, an amplifier circuit, a power converter circuit, or an optocoupler circuit.

4. The electronic device packaging as in claim 2 , wherein, when the one or more electronic components includes the second circuit element, the second circuit element includes a diode, a light-emitting diode (LED), a transistor, a battery, or an impedance element.

5. The electronic device packaging as in claim 2 , wherein, when the one or more electronic components includes the microchip, the microchip includes a bare die microchip or a thin film microchip.

6. The electronic device packaging as in claim 1 , wherein the flexible and electrically insulative material includes polyimide, silicone-base elastomers, benzocyclobutane (BCB), SU-8, or elastomer containing additive conductive particles including carbon particles, carbon nanotubes, or Si nanowires.

7. The electronic device packaging as in claim 1 , further comprising:
a template structure including an electrically insulative material and structured to include a contact side to attach to the side of the substrate, wherein the template structure includes one or more cavities formed on the contact side in particular positions to encompass the corresponding one or more electronic components to be adhered on the substrate.

8. The electronic device packaging as in claim 7 , wherein a second side of the template structure opposite the contact side of the template structure is a flat surface.

9. The electronic device packaging as in claim 1 , wherein the substrate includes an optically cured polymer.

10. The electronic device packaging as in claim 1 , wherein the interconnection wires include an active electronic component.

11. An electronic device packaging, comprising:
a substrate formed from a material that is both flexible and electrically insulative, wherein the substrate includes a side on which one or more electronic components can adhere, wherein the substrate includes openings spanning from the side into an interior region of the substrate, and wherein the openings are arranged to align to locations where conductive contacts of the one or more electronic components are designed to be positioned;
interconnection wires including an electrically conductive material, the interconnection wires disposed in the openings and the interior region of the substrate in a particular arrangement based on an electronic device design to electrically connect the one or more electronic components, wherein an interconnection portion of the interconnection wires are configured in a planar layer in the interior region;
a second layer of additional interconnection wires disposed in the interior region of the substrate and electrically coupled to at least some of the interconnection wires, wherein an additional interconnection portion of the additional interconnection wires are configured in a second planar layer in the interior region; and
a circuit element disposed in the interior region of the substrate at the planar layer or the second planar layer and in electrical connection with at least one interconnection wire of the interconnection wires, the circuit element including one or more of a resistor, capacitor, inductor, antenna, or transmission line,
wherein the substrate is structured to have a thickness less than 35 μm
wherein the electronic device packaging has a two-dimensional footprint that is 100 μm or less outside of a footprint of the one or more electronic components that can adhere to the side of the substrate.

12. The electronic device packaging as in claim 11 , wherein the one or more electronic components to adhere to the substrate include a second circuit element, a circuit, or a microchip.

13. The electronic device packaging as in claim 12 , wherein, when the one or more electronic components includes the circuit, the circuit includes an integrated circuit, a thin film circuit, a sensor circuit, a transducer circuit, an amplifier circuit, a power converter circuit, or an optocoupler circuit.

14. The electronic device packaging as in claim 12 , wherein, when the one or more electronic components includes the second circuit element, the second circuit element includes a diode, a light-emitting diode (LED), a transistor, a battery, or an impedance element.

15. The electronic device packaging as in claim 12 , wherein, when the one or more electronic components includes the microchip, the microchip includes a bare die microchip or a thin film microchip.

16. The electronic device packaging as in claim 11 , wherein the flexible and electrically insulative material includes polyimide, silicone-base elastomers, benzocyclobutane (BCB), SU-8, or elastomer containing additive conductive particles including carbon particles, carbon nanotubes, or Si nanowires.

17. The electronic device packaging as in claim 11 , further comprising:
a template structure including an electrically insulative material and structured to include a contact side to attach to the side of the substrate, wherein the template structure includes one or more cavities formed on the contact side in particular positions to encompass the corresponding one or more electronic components to be adhered on the substrate.

18. The electronic device packaging as in claim 17 , wherein a second side of the template structure opposite the contact side of the template structure is a flat surface.

19. The electronic device packaging as in claim 11 , wherein the substrate includes an optically cured polymer.

20. The electronic device pac

Assignees

• Univ California

Inventors

• Coleman Todd Prentice
• Kim Yun Soung
• Bajema Michael
• Weinreb Robert N

Classifications

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/654

  Top-view layouts · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W74/01

  Manufacture or treatment · CPC title