Image sensors and image processing systems using multilevel signaling techniques

Patent metadata

Field	Value
Publication number	US-10506189-B2
Application number	US-201514728355-A
Country	US
Kind code	B2
Filing date	Jun 2, 2015
Priority date	Jun 11, 2014
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

An image sensor includes a pixel array configured to generate a plurality of pixel signals, an analog to digital converter circuit coupled to the pixel array and configured to generate respective digital codes responsive to respective ones of the pixel signals, a plurality of memories, respective ones of which are configured to store respective bits of the digital codes, a signal processing circuit coupled to a plurality of memories and configured to generate analog signals responsive to the stored bits, each of the analog signals corresponding to multiple ones of the stored bits, and a comparator circuit configured to compare the analog signals to respective ones of a plurality of reference signals to generate digital signals corresponding to the multiple ones of the stored bits. Related image processing systems and methods are also described.

First claim

What is claimed is:

1. An image sensor comprising:
a plurality of 1-bit storage devices, respective ones of which are configured to store respective ones of a plurality of 1-bit signals;
a signal generator configured to generate weighted sum signals responsive to the 1-bit signals stored in the 1-bit storage devices, the weighted sum signals having at least three different levels corresponding to respective values of the 1-bit signals stored in the 1-bit storage devices; and
a comparator array configured to compare each of a plurality of reference signals with the weighted sum signals and to responsively generate a plurality of digital signals, and
wherein each of the weighted sum signals is generated based on values of at least two 1-bit signals which are stored in at least two different 1-bit storage devices, respectively.

2. The image sensor of claim 1 , further comprising:
a plurality of pixels configured to generate respective pixel signals; and
a plurality of analog-to-digital converters configured to convert respective ones of the pixel signals into respective digital codes,
wherein respective ones of the 1-bit signals are included in respective ones of the digital codes and the 1-bit signals are at the same bit positions in the digital codes.

3. The image sensor of claim 2 , further comprising a column address decoder configured to decode a single column address and to simultaneously activate a plurality of column selection signals, wherein the signal generator generates the weighted sum signals using the column selection signals and the 1-bit signals.

4. The image sensor of claim 1 , further comprising:
a pixel configured to output a pixel signal; and
an analog-to-digital converter configured to convert the pixel signal into a digital code,
wherein the 1-bit signals are included in the digital code and adjacent to each other in the digital code.

5. The image sensor of claim 1 , wherein the comparator array comprises:
a plurality of comparators, respective ones of which are configured compare respective ones of the reference signals with the weighted sum signal; and
a decoder configured to decode comparison signals output from the comparators to generate the digital signals.

6. An image processing system comprising:
an image sensor comprising:
a plurality of 1-bit storage devices configured to store respective ones of a plurality of 1-bit signals;
a signal generator configured to generate weighted sum signals responsive to the 1-bit signals stored in the 1-bit storage devices, the weighted sum signals having at least 3 different levels corresponding to respective values of the 1-bit signals stored in the 1-bit storage devices;
a comparator array configured to compare respective ones of a plurality of reference signals with the weighted sum signals and to responsively generate a plurality of digital signals; and
a processor configured to control the image sensor, and
wherein each of the weighted sum signals is generated based on values of at least two 1-bit signals which are stored in at least two different 1-bit storage devices respectively.

7. The image processing system of claim 6 , wherein the image sensor and the processor are configured to communicate via a camera serial interface (CSI).

8. The image processing system of claim 6 , further comprising:
a plurality of pixels, respective ones of which are configured to generate respective ones of a plurality of pixels signals; and
a plurality of analog-to-digital converters, respective ones of which are configured to convert respective ones of the pixel signals into digital codes,
wherein respective ones of the 1-bit signals are included in respective ones of the digital codes and the 1-bit signals are at the same bit positions in the digital codes.

9. The image processing system of claim 6 , further comprising a column address decoder configured to decode a single column address and simultaneously generate a plurality of column selection signals, wherein the signal generator generates the weighted sum signals using the column selection signals and the 1-bit signals.

10. The image processing system of claim 6 , further comprising a column address decoder configured to decode a column address and generate a column selection signal, wherein the signal generator generates the weighted sum signals using the column selection signal and the 1-bit signals.

11. The image processing system of claim 6 , further comprising:
a pixel configured to output a pixel signal; and
an analog-to-digital converter configured to convert the pixel signal into a digital code,
wherein the 1-bit signals are part of the digital code and adjacent to each other in the digital code.

12. The image processing system of claim 6 , wherein the comparator array comprises:
a plurality of comparators, respective ones of which are configured to compare respective ones of the reference signals with the weighted sum signals; and
a decoder configured to decode comparison signals output from the comparators to generate the digital signals.

13. The image processing system of claim 6 , wherein the signal generator adjusts coefficients related to the levels according to control of the processor.

14. An image sensor comprising:
a pixel array configured to generate a plurality of pixel signals;
an analog to digital converter circuit coupled to the pixel array and configured to generate respective digital codes responsive to respective ones of the pixel signals;
a plurality of memories, respective ones of which are configured to store respective bits of the digital codes;
a signal processing circuit coupled to a plurality of memories and configured to generate analog signals responsive to the stored bits of the digital codes, each of the analog signals corresponding to multiple ones of the stored bits and having levels corresponding to respective values of the multiple ones of the stored bits; and
a comparator circuit configured to compare the analog signals to respective ones of a plurality of reference signals to generate digital signals corresponding to the multiple ones of the stored bits, and
wherein each of the analog signals is generated based on values of at east two stored bits.

15. The image sensor of claim 14 , wherein each of the analog signals correspond to multiple bits from two or more of the digital codes.

16. The image sensor of claim 14 , wherein each of the analog signals corresponds to multiple bits from one of the digital codes.

17. The image sensor of claim 14 , further comprising an address decoder configured to select at least two of the memories responsive to a given address to provide multiple bits to the signal processing circuit, wherein the signal processing circuit is configured to generate one of the analog signals responsive to the provided multiple bits.

18. The image sensor of claim 17 , wherein the address decoder is configured to simultaneously select memories corresponding to at least two of the digital codes responsive to a given address to provide the multiple bits to the signal processing circuit from multiple ones of the digital codes.

19. The image sensor of claim 17 , wherein the address decoder is configured to simultaneously select memories corresponding to one of the digital codes responsive to a given address to provide the multiple bits to the signal processing circuit from the one of the digital codes.

20. The image sensor of claim 14 , wherein a number of bits corresponding to the respective analog signals is T, a n

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoo Kwi Sung
• Jin Eun Young

Classifications

• H04N23/76 Primary

  by influencing the image signals · CPC title

• H04N5/378

  Electricity · mapped topic

• H04N5/37455 Primary

  Electricity · mapped topic

• H04N5/243

  Electricity · mapped topic

• H04N25/78 Primary

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title