Clock recovery for band-limited optical channels

Patent metadata

Field	Value
Publication number	US-10505641-B2
Application number	US-201815966697-A
Country	US
Kind code	B2
Filing date	Apr 30, 2018
Priority date	Apr 30, 2018
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

A coherent optical receiver in which the channel equalizer and the clock-recovery circuit are connected in a nested-loop configuration, wherein the channel estimate generated by the equalizer is used to adjust the phase of the clock signal generated by the clock-recovery circuit. The channel equalizer can be implemented using a bank of time-domain or frequency-domain FIR filters. In an example embodiment, the clock-recovery circuit is configured to track the phase rotation corresponding to the equalized signals in a frequency-dependent manner; track the phase rotation in the channel equalizer either in a frequency-dependent manner or based on the mean signal delay therein; and adjust the phase of the clock signal based on an effective difference between these two phase rotations. The clock-recovery circuit enhances the clock tone by applying a Fourier transform to the squared absolute values of the equalized signals outputted by the channel equalizer.

First claim

What is claimed is:

1. An apparatus comprising an optical data receiver that comprises:
an optical front end that comprises:
an optical hybrid configured to mix an optical data signal and an optical local-oscillator signal to generate a plurality of mixed optical signals; and
a plurality of photodetectors configured to generate a plurality of electrical digital measures of the optical data signal in response to the mixed optical signals; and

a digital signal processor that comprises:
a digital equalizing filter configured to generate a second plurality of digital samples by digitally filtering a first plurality of digital samples, said filtering being based on a transfer function, said first plurality of digital samples being generated in response to the plurality of electrical digital measures and a clock signal, the digital equalizing filter being configured to generate a control signal carrying a plurality of values representing the transfer function;
a clock-recovery circuit configured to generate the clock signal using at least some of the second plurality of digital samples and in response to the control signal generated by the digital equalizing filter; and
a signal decoder configured to recover data encoded in the optical data signal using the second plurality of digital samples.

2. The apparatus of claim 1 , wherein the digital signal processor further comprises a signal interpolator configured to generate the first plurality of digital samples by interpolating one or more digital signals representing the plurality of electrical digital measures, said interpolating being performed using the clock signal.

3. The apparatus of claim 1 ,
wherein the digital equalizing filter is configured to generate a first stream of digital samples and a second stream of digital samples by applying the transfer function to the first plurality of digital samples; and
wherein the second plurality of digital samples includes the first and second streams of digital samples.

4. The apparatus of claim 3 ,
wherein the first stream of digital samples comprises digital samples corresponding to a first polarization of the optical data signal; and
wherein the second stream of digital samples comprises digital samples corresponding to a second polarization of the optical data signal that is orthogonal to the first polarization.

5. The apparatus of claim 3 , wherein the clock-recovery circuit is configured to generate the clock signal in response to a selected one of the first and second streams of digital samples.

6. The apparatus of claim 1 , wherein the clock-recovery circuit is further configured to generate the clock signal in response to the at least some of the second plurality of digital samples.

7. The apparatus of claim 1 , wherein the digital equalizing filter is configured to generate the control signal such that the plurality of values includes two or more sets of complex values, each set representing a respective matrix element of the transfer function as a function of frequency.

8. The apparatus of claim 1 , wherein the digital equalizing filter is configured to generate the control signal such that the plurality of values includes two or more sets of finite-impulse-response-filter tap coefficients, each set representing a respective matrix element of the transfer function.

9. The apparatus of claim 1 , wherein the clock-recovery circuit is configured to:
generate a first estimate of phase rotation using the second plurality of digital samples;
generate a second estimate of phase rotation, the second estimate being an estimate of phase rotation in the digital equalizing filter;
generate a third estimate of phase rotation, the third estimate representing a frequency offset between the clock signal and a clock of the optical data signal, the third estimate being generated using the first and second estimates; and
adjust a phase of the clock signal using the third estimate.

10. The apparatus of claim 1 , wherein the clock-recovery circuit comprises:
a squaring circuit configured to generate squared absolute values of some of the second plurality of digital samples;
a discrete-Fourier-transform circuit configured to generate a plurality of spectral samples by applying a Fourier transform to the squared absolute values;
a first digital circuit configured to generate an estimate of phase rotation in the digital equalizing filter in response to the control signal; and
a second digital circuit configured to adjust a phase of the clock signal using the plurality of spectral samples and the estimate of phase rotation.

11. The apparatus of claim 10 , wherein the first digital circuit is configured to generate the estimate of phase rotation using a determinant of the transfer function.

12. The apparatus of claim 1 , wherein the clock-recovery circuit comprises:
a squaring circuit configured to generate squared absolute values of a subset of the second plurality of digital samples;
a discrete-Fourier-transform circuit configured to generate a plurality of spectral samples by applying a Fourier transform to the squared absolute values;
a delay-estimator circuit configured to generate an estimate of signal delay in the digital filter in response to receiving the control signal; and
a digital circuit configured to adjust a phase of the clock signal using the plurality of spectral samples and the estimate of signal delay.

13. The apparatus of claim 1 , wherein the digital equalizing filter comprises a multiple-input/multiple-output channel equalizer.

14. The apparatus of claim 13 , wherein the channel equalizer is configured to perform at least some of the following:
electronic polarization demultiplexing; and
digital filtering configured to reduce signal distortions caused by one or more of polarization-mode dispersion, polarization-dependent loss, inter-symbol interference, and chromatic dispersion.

15. The apparatus of claim 1 ,
wherein the clock-recovery circuit comprises a first discrete-Fourier-transform circuit configured to generate L spectral samples by applying a Fourier transform to a corresponding set of input values, where L is a positive integer greater than one; and
wherein the digital equalizing filter comprises a finite-impulse-response filter of length M, where M is a positive integer that is different form L.

16. The apparatus of claim 15 , wherein the clock-recovery circuit comprises a second discrete-Fourier-transform circuit configured to apply a zero-fill operation to a set of M input values to generate a corresponding set of L spectral samples, where L>M.

17. The apparatus of claim 1 , wherein the digital signal processor further comprises:
a signal interpolator configured to generate the first plurality of digital samples by interpolating one or more digital signals representing the plurality of electrical digital measures; and
a feedback circuit path that connects one or more outputs of the digital equalizing filter and the signal interpolator, the feedback circuit path including the clock-recovery circuit.

18. An apparatus comprising a digital signal processor that comprises:
a digital equalizing filter configured to generate a second plurality of digital samples by digitally filtering a first plurality of digital samples, said filtering being based on a transfer function, said first plurality of digital samples corresponding to an input data signal and being generated using a clock signal, the digital equalizing filter being configured to generate a control signal carrying a plurality of values representing the tr

Assignees

• Nokia Solutions & Networks Oy

Inventors

• Kaneda Noriaki
• Weisser Stephan
• Costantini Carlo

Classifications

• H04B10/63

  Homodyne {, i.e. coherent receivers where the local oscillator is locked in frequency and phase to the carrier signal} · CPC title

• H04B10/614

  comprising one or more polarization beam splitters, e.g. polarization multiplexed [PolMux] X-PSK coherent receivers, polarization diversity heterodyne coherent receivers (H04J14/06 takes precedence) · CPC title

• H04B10/6164

  Estimation or correction of the frequency offset between the received optical signal and the optical local oscillator · CPC title

• H04B10/6161 Primary

  Compensation of chromatic dispersion · CPC title

• H04B10/6162

  Compensation of polarization related effects, e.g., PMD, PDL · CPC title