Radio frequency device packages and methods of formation thereof

Patent metadata

Field	Value
Publication number	US-10505255-B2
Application number	US-201715419225-A
Country	US
Kind code	B2
Filing date	Jan 30, 2017
Priority date	Jan 30, 2017
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

A semiconductor device package includes a radio frequency front end circuit configured to process radio frequency signals, a first antenna, an antenna substrate, and a first conductive barrier. The first antenna is configured to transmit/receive a first radio frequency signal. The antenna substrate includes the first antenna. The antenna substrate is configured to transfer the first radio frequency signal between the radio frequency front end circuit and the first antenna. The first conductive barrier is configured to electromagnetically and electrostatically isolate the first antenna.

First claim

What is claimed is:

1. A semiconductor device package comprising:
a radio frequency front end circuit configured to process radio frequency signals;
an antenna substrate comprising a first conductive layer, a first insulating layer disposed over the first conductive layer, a second conductive layer disposed over the first insulating layer, a second insulating layer disposed over the second conducive layer, a third conductive layer disposed over the second insulating layer, a third insulating layer disposed over the third conductive layer, and a fourth conductive layer disposed over the third insulating layer;
a first antenna disposed in the antenna substrate and configured to transmit/receive a first radio frequency signal, the first antenna comprising a first peripheral ground plane section in the first conductive layer, a first antenna feedline portion in the second conductive layer that is operatively coupled to the radio frequency front end circuit, a first interior ground plane in the third conductive layer, and a first patch antenna portion in the fourth conductive layer, wherein the first interior ground plane comprises an opening disposed over the first antenna feedline portion;
a first conductive barrier configured to electromagnetically and electrostatically isolate the first antenna, the first conductive barrier extending from the first conductive layer to the fourth conductive layer;
a second antenna disposed in the antenna substrate and configured to transmit/receive a second radio frequency signal, the second antenna comprising a second peripheral ground plane section in the first conductive layer, a second antenna feedline portion in the second conductive layer that is operatively coupled to the radio frequency front end circuit, a second interior ground plane in the third conductive layer, and a second patch antenna portion in the fourth conductive layer, wherein the second interior ground plane comprises an opening disposed over the second antenna feedline portion; and
a second conductive barrier configured to electromagnetically and electrostatically isolate the second antenna from the first antenna, wherein the second conductive barrier extends from the first conductive layer to the fourth conductive layer, the second conductive barrier is disposed along a periphery of the second antenna, and a first edge of the first conductive barrier closest to the second antenna is spaced apart from a first edge of the second conductive barrier closest to the first antenna.

2. The semiconductor device package of claim 1 , wherein the first antenna is configured only to receive the first radio frequency signal and wherein the second antenna is configured only to transmit the second radio frequency signal.

3. The semiconductor device package of claim 1 , wherein the radio frequency signals comprise a frequency between 55 GHz and 65 GHz, and wherein a gain of the first antenna is about 6 dBi.

4. A semiconductor device package comprising:
an integrated circuit chip comprising a radio frequency front end circuit for transmitting/receiving radio frequency signals; and
an antenna substrate disposed over a first surface of the integrated circuit chip, the antenna substrate comprising
a first conductive layer,
a first insulating layer disposed over the first conductive layer,
a second conductive layer disposed over the first insulating layer,
a second insulating layer disposed over the second conducive layer,
a third conductive layer disposed over the second insulating layer,
a third insulating layer disposed over the third conductive layer, and
a fourth conductive layer disposed over the third insulating layer,
a first antenna disposed in the antenna substrate, the first antenna comprising a first peripheral ground plane section in the first conductive layer, a first antenna feedline portion in the second conductive layer that is operatively coupled to the radio frequency front end circuit, a first interior ground plane in the third conductive layer, and a first patch antenna portion in the fourth conductive layer, wherein the first interior ground plane comprises an opening disposed over the first antenna feedline portion,
a first conductive barrier with sides extending in a direction perpendicular to a first surface of the antenna substrate, wherein the first conductive barrier is disposed along a periphery of the first antenna, the first conductive barrier extending from the first conductive layer to the fourth conductive layer,
a second antenna disposed in the antenna substrate, the second antenna comprising a second peripheral ground plane section in the first conductive layer, a second antenna feedline portion in the second conductive layer that is operatively coupled to the radio frequency front end circuit, a second interior ground plane in the third conductive layer, and a second patch antenna portion in the fourth conductive layer, wherein the second interior ground plane comprises an opening disposed over the second antenna feedline portion, and
a second conductive barrier with sides extending in the direction perpendicular to the first surface of the antenna substrate, wherein the second conductive barrier extends from the first conductive layer to the fourth conductive layer, the second conductive barrier is disposed along a periphery of the second antenna, wherein a first edge of the first conductive barrier closest to the second antenna is spaced apart from a first edge of the second conductive barrier closest to the first antenna.

5. The semiconductor device package of claim 4 , wherein the first conductive barrier extends from the first surface of the antenna substrate to a second surface of the antenna substrate in the direction perpendicular to the first surface of the antenna substrate.

6. The semiconductor device package of claim 4 , wherein the first conductive barrier is along at least two adjacent sides of the first antenna.

7. The semiconductor device package of claim 4 , wherein the first conductive barrier surrounds all sides of the first antenna.

8. The semiconductor device package of claim 4 , wherein the first conductive barrier comprises metal line segments.

9. The semiconductor device package of claim 4 , wherein the first conductive barrier comprises a first plurality of vias extending in the direction perpendicular to the first surface of the antenna substrate, the first plurality of vias disposed around the first antenna.

10. The semiconductor device package of claim 9 , wherein
the first plurality of vias are disposed along a first side of the first antenna,
along the first side, a first subset of the first plurality of vias is disposed along a first row, and
along the first side, a second subset of the first plurality of vias is disposed along a second row different from the first row.

11. The semiconductor device package of claim 9 , wherein a spacing between adjacent vias of the first plurality of vias is substantially constant.

12. The semiconductor device package of claim 9 , wherein the second conductive barrier comprises a second plurality of vias extending in the direction perpendicular to the first surface of the antenna substrate, and the second plurality of vias are disposed around the second antenna.

13. The semiconductor device package of claim 4 , wherein the second conductive barrier is along at least two adjacent sides of the second antenna.

14. The semiconductor device package of claim 13 , wherein the second conductive barrier surrounds all sides of the second antenna.

15. The semiconductor device package of claim 4 , wherein the second conductive b

Assignees

• Infineon Technologies Ag

Inventors

• Baheti Ashutosh
• Trotta Saverio
• Reiss Werner

Classifications

• H01Q1/523

  between antennas of an array · CPC title

• H01Q9/0457

  electromagnetically coupled to the feed line · CPC title

• H10W44/248

  for antennas · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title