Balun

Patent metadata

Field	Value
Publication number	US-10505243-B2
Application number	US-201715786111-A
Country	US
Kind code	B2
Filing date	Oct 17, 2017
Priority date	Oct 28, 2016
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

A balun includes an unbalanced port, a first balanced port, a second balanced port, a main line, a subline, a capacitor, and an impedance matching section. The subline is configured to be electromagnetically coupled to the main line. The main line has a first end and a second end opposite to each other. The subline has a first end and a second end opposite to each other. The capacitor is provided between the first end of the main line and the unbalanced port. The impedance matching section is provided between the second end of the subline and the second balanced port. The second end of the main line is connected to a ground. The first end of the subline is connected to the first balanced port.

First claim

What is claimed is:

1. A balun comprising:
an unbalanced port;
a first balanced port;
a second balanced port;
a main line having a first end and a second end opposite to each other, the second end of the main line being connected to a ground;
a subline configured to be electromagnetically coupled to the main line and having a first end and a second end opposite to each other, the first end of the subline being directly connected to the first balanced port;
a first capacitor provided between the first end of the main line and the unbalanced port; and
an impedance matching section provided between the second end of the subline and the second balanced port, wherein
the impedance matching section includes a first path connecting the second end of the subline and the second balanced port, and a second path connecting the first path and the ground,
the first path includes an inductor, and
the second path includes a second capacitor.

2. The balun according to claim 1 , further comprising a multilayer structure for integrating the unbalanced port, the first and second balanced ports, the main line, the subline, the first capacitor and the impedance matching section, the multilayer structure including a plurality of dielectric layers and a plurality of conductor layers stacked on each other.

3. A balun comprising:
an unbalanced port;
a first balanced port;
a second balanced port;
a main line having a first end and a second end opposite to each other, the second end of the main line being connected to a ground;
a subline configured to be electromagnetically coupled to the main line and having a first end and a second end opposite to each other, the first end of the subline being directly connected to the first balanced port;
a first capacitor provided between the first end of the main line and the unbalanced port; and
an impedance matching section provided between the second end of the subline and the second balanced port, wherein
the impedance matching section includes a first path connecting the second end of the subline and the second balanced port, and a second path connecting the first path and the ground,
the first path includes a first inductance element and a second inductance element having their respective inductances and configured to be inductively coupled to each other,
each of the first and second inductance elements has a first end and a second end opposite to each other,
the first end of the first inductance element is connected to the second end of the subline,
the first end of the second inductance element is connected to the second balanced port,
the second end of the first inductance element and the second end of the second inductance element are connected to each other, and connected to the ground via the second path, and
the second path includes a second capacitor.

4. The balun according to claim 3 , further comprising a multilayer structure for integrating the unbalanced port, the first and second balanced ports, the main line, the subline, the first capacitor and the impedance matching section, the multilayer structure including a plurality of dielectric layers and a plurality of conductor layers stacked on each other.

5. The balun according to claim 3 , wherein the first inductance element is a first line, and the second inductance element is a second line.

6. The balun according to claim 5 , wherein the first line and the second line are configured to be capacitively coupled to each other.

7. The balun according to claim 5 , wherein
the first line includes a first line portion,
the second line includes a second line portion opposed to the first line portion,
the first line portion has a first edge and a second edge opposite to each other, the first edge of the first line portion being closest to the second end of the subline in circuit configuration,
the second line portion has a first edge and a second edge opposite to each other, the first edge of the second line portion being closest to the second balanced port in circuit configuration,
the first edge of the second line portion is physically closer to the second edge of the first line portion than to any other part of the first line portion, and
the second edge of the second line portion is physically closer to the first edge of the first line portion than to any other part of the first line portion.

8. A balun comprising:
an unbalanced port;
a first balanced port;
a second balanced port;
a main line having a first end and a second end opposite to each other, the second end of the main line being connected to a ground;
a subline configured to be electromagnetically coupled to the main line and having a first end and a second end opposite to each other, the first end of the subline being connected to the first balanced port;
a first capacitor provided between the first end of the main line and the unbalanced port; and
an impedance matching section provided between the second end of the subline and the second balanced port, the impedance matching section including:
a first path connecting the second end of the subline and the second balanced port, the first path including:
a first inductance element having a first inductance, the first inductance element including:
a first end connected to the second end of the subline; and
a second end opposite to the first end of the first inductance element; and

a second inductance element having a second inductance, and configured to be inductively coupled to the first inductance element, the second inductance element including:
a first end connected to the second balanced port; and
a second end opposite to the first end of the second inductance element, the second end of the second inductance element being connected to the second end of the first inductance element; and

a second path connecting the first path and the ground, the second path including a second capacitor,

wherein the second end of the first inductance element and the second end of the second inductance element are connected to the ground via the second path.

9. The balun according to claim 8 , wherein the first inductance element is a first line, and the second inductance element is a second line.

10. The balun according to claim 9 , wherein the first line and the second line are configured to be capacitively coupled to each other.

11. The balun according to claim 9 , wherein
the first line includes a first line portion,
the second line includes a second line portion opposed to the first line portion,
the first line portion has a first edge and a second edge opposite to each other, the first edge of the first line portion being closest to the second end of the subline in circuit configuration,
the second line portion has a first edge and a second edge opposite to each other, the first edge of the second line portion being closest to the second balanced port in circuit configuration,
the first edge of the second line portion is physically closer to the second edge of the first line portion than to any other part of the first line portion, and
the second edge of the second line portion is physically closer to the first edge of the first line portion than to any other part of the first line portion.

Assignees

• Tdk Corp

Inventors

• Suzuki Hiroya
• Ashida Yuta
• Ootsuka Noriaki

Classifications

• H01Q5/335

  at the feed, e.g. for impedance matching · CPC title

• H03B5/1265

  switched capacitors · CPC title

• H03H7/38

  Impedance-matching networks · CPC title

• H01P1/022 Primary

  in waveguides of polygonal cross-section (H01P1/065 takes precedence) · CPC title

• H01P5/10 Primary

  for coupling balanced lines or devices with unbalanced lines or devices · CPC title