Tri-layer semiconductor stacks for patterning features on solar cells

Patent metadata

Field	Value
Publication number	US-10505068-B2
Application number	US-201916284988-A
Country	US
Kind code	B2
Filing date	Feb 25, 2019
Priority date	Apr 1, 2016
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.

First claim

What is claimed is:

1. A method of fabricating a solar cell, the method comprising:
forming a first semiconductor layer above a substrate;
forming a P-type semiconductor layer directly on the first semiconductor layer;
forming a third semiconductor layer directly on the P-type semiconductor layer;
forming a mask layer directly on the third semiconductor layer;
patterning the mask layer;
etching the third semiconductor layer, the P-type semiconductor layer, and the first semiconductor layer to provide a semiconductor structure having an outermost edge of the third semiconductor layer laterally recessed from an outermost edge of the first semiconductor layer by a width, and an outermost edge of the P-type semiconductor layer sloped from the outermost edge of the first semiconductor layer to the outermost edge of the third semiconductor layer;
wherein the first semiconductor layer is a first intrinsic silicon layer, the P-type semiconductor layer is a boron-doped silicon layer, and the third semiconductor layer is a second intrinsic silicon layer.

2. The method of claim 1 , further comprising:
laser ablating an opening in the mask layer to expose a portion of the semiconductor structure.

3. The method of claim 2 , further comprising:
forming a conductive contact structure in the opening.

4. The method of claim 3 , further comprising:
prior to forming the conductive contact structure, annealing the semiconductor structure.

5. The method of claim 2 , wherein the laser ablating penetrates a portion of the third semiconductor layer but does not penetrate through to the P-type semiconductor layer.

6. The method of claim 1 , wherein etching the third semiconductor layer, the P-type semiconductor layer, and the first semiconductor layer comprising using a wet etchant selected from the group consisting of an aqueous solution of TMAH and an aqueous solution of KOH.

7. A method of fabricating a solar cell, the method comprising:
forming a semiconductor structure above a substrate, the semiconductor structure comprising a P-type semiconductor layer formed directly on a first semiconductor layer, and a third semiconductor layer formed directly on the P-type semiconductor layer, wherein an outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width, and wherein an outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the first semiconductor layer to the outermost edge of the third semiconductor layer; and
forming a conductive contact structure electrically connected to the semiconductor structure, wherein the semiconductor structure is vertically stacked with the first semiconductor layer between the P-type semiconductor layer and the substrate, the P-type semiconductor layer between the first and third semiconductor layers, and the third semiconductor layer between the P-type semiconductor layer and the conductive contact structure;
wherein the first semiconductor layer is a first intrinsic silicon layer, the P-type semiconductor layer is a boron-doped silicon layer, and the third semiconductor layer is a second intrinsic silicon layer.

8. The method of claim 7 , wherein the first semiconductor layer has a thickness approximately equal to a thickness of the P-type semiconductor layer and approximately equal to a thickness of the third semiconductor layer.

9. The method of claim 7 , wherein the P-type semiconductor layer has a thickness greater than approximately 10% but less than approximately 90% of a total thickness of the semiconductor structure.

10. The method of claim 7 , wherein none of the first semiconductor layer, the P-type semiconductor layer, and the third semiconductor layer has a thickness less than approximately 10% of a total thickness of the semiconductor structure.

11. The method of claim 10 , wherein the first intrinsic silicon layer, the P-type semiconductor layer, and the second intrinsic silicon layer are amorphous layers.

12. The method of claim 10 , wherein the first intrinsic silicon layer, the P-type semiconductor layer, and the second intrinsic silicon layer are polycrystalline layers.

13. The method of claim 10 , wherein the first intrinsic silicon layer and the second intrinsic silicon layers each have a total dopant concentration of less than approximately 1E18 atoms/cm 3 , and the P-type semiconductor layer has a total boron concentration of greater than approximately 2E19 atoms/cm 3 .

14. The method of claim 7 , wherein the semiconductor structure is formed on a tunneling dielectric layer formed on the substrate.

15. The method of claim 7 , wherein the conductive contact structure is formed in an opening of an anti-reflective coating layer formed over the semiconductor structure.

16. The method of claim 7 , wherein the semiconductor structure is an emitter region of the solar cell.

17. A method of fabricating a solar cell, the method comprising:
forming a semiconductor structure above a substrate, the semiconductor structure comprising a second semiconductor layer formed directly on a first semiconductor layer, and a third semiconductor layer formed directly on the second semiconductor layer, wherein an outermost edge of the third semiconductor layer has a non-reentrant profile, an outermost edge of the second semiconductor layer has a non-reentrant profile extending beyond the outermost edge of the third semiconductor layer by a width, and an outermost edge of the first semiconductor layer has a non-reentrant profile and does not undercut the second semiconductor layer, and wherein the non-reentrant profiles of the first and third semiconductor layers are steeper than the non-reentrant profile of the second semiconductor layer; and
forming a conductive contact structure electrically connected to the semiconductor structure, wherein the semiconductor structure is vertically stacked with the first semiconductor layer between the second semiconductor layer and the substrate, the second semiconductor layer between the first and third semiconductor layers, and the third semiconductor layer between the second semiconductor layer and the conductive contact structure;
wherein the first semiconductor layer is a first intrinsic silicon layer, the second semiconductor layer is a P-type boron doped silicon layer, and the third semiconductor layer is a second intrinsic silicon layer.

18. The method of claim 17 , wherein the first and the third semiconductor layers each have a total dopant concentration of less than approximately 1E18 atoms/cm 3 , and the P-type silicon layer has a total boron concentration of greater than approximately 2E19 atoms/cm 3 .

19. The method of claim 17 , wherein the first semiconductor layer has a thickness approximately equal to a thickness of the third semiconductor layer.

20. The method of claim 17 , wherein the second semiconductor layer has a thickness greater than approximately 10% but less than approximately 90% of a total.

Assignees

• Sunpower Corp

Inventors

• Tracy Kieran Mark
• Smith David D
• Balu Venkatasubramani
• Masad Asnat
• Waldhauer Ann

Classifications

• Y02E10/547

  Monocrystalline silicon PV cells · CPC title

• H01L31/035281

  Electricity · mapped topic

• H01L31/202

  Electricity · mapped topic

• H01L31/0682

  Electricity · mapped topic

• H01L31/18

  Electricity · mapped topic