P-channel DEMOS device

Patent metadata

Field	Value
Publication number	US-10505037-B2
Application number	US-201815915529-A
Country	US
Kind code	B2
Filing date	Mar 8, 2018
Priority date	Apr 21, 2016
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

A p-channel drain extended metal oxide semiconductor (DEPMOS) device includes a doped surface layer at least one nwell finger defining an nwell length and width direction within the doped surface layer. A first pwell is on one side of the nwell finger including a p+ source and a second pwell is on an opposite side of the nwell finger including a p+ drain. A gate stack defines a channel region of the nwell finger between the source and drain. A field dielectric layer is on a portion of the doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along the width direction (WD boundary). The nwell finger includes a reduced doping finger edge region over a portion of the WD boundary.

First claim

The invention claimed is:

1. A p-channel drain extended metal oxide semiconductor (DEPMOS) device, comprising:
a substrate having a doped surface layer thereon;
at least one nwell finger defining a nwell length direction and an nwell width direction having nwell doping formed within said doped surface layer;
a first pwell on one side of said nwell finger including a p+ source therein and a second pwell on an opposite side of said nwell finger including a p+ drain;
a gate stack defining a channel region of said nwell finger between said source and said drain including a gate dielectric layer and a patterned gate electrode on said gate dielectric layer;
a field dielectric layer on a portion of said doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along said width direction (WD boundary),
wherein said nwell finger includes a reduced doping finger edge region over a portion of said WD boundary.

2. The DEPMOS of claim 1 , wherein said field dielectric layer comprises a Local Oxidation of Silicon (LOCOS) oxide.

3. The DEPMOS of claim 1 , wherein said reduced doping finger edge region comprises a region counterdoped with a p-type dopant.

4. The DEPMOS of claim 1 , wherein said reduced doping finger edge region comprises a region lacking said nwell doping.

5. The DEPMOS of claim 1 , wherein said reduced doping finger edge region extends a total of between 1 μm and 4 μm in said nwell length direction, and is recessed from an edge of said nwell finger in said nwell width direction.

6. The DEPMOS of claim 1 , wherein said at least one nwell finger comprises a plurality of said nwell fingers.

7. The DEPMOS of claim 1 , wherein said DEPMOS device has a symmetric drain structure.

8. An integrated circuit (IC) comprising a substrate including a doped surface layer thereon having a p-channel drain extended metal oxide semiconductor (DEPMOS) device formed in said doped surface layer, said DEPMOS device comprising:
at least one nwell finger defining a nwell length direction and an nwell width direction having nwell doping formed within said doped surface layer;
a first pwell on one side of said nwell finger including a p+ source therein and a second pwell on an opposite side of said nwell finger including a p+ drain;
a gate stack defining a channel region of said nwell finger between said source and said drain including a gate dielectric layer and a patterned gate electrode on said gate dielectric layer, and
a field dielectric layer on a portion of said doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along said width direction (WD boundary),
wherein said nwell finger includes a reduced doping finger edge region over a portion of said WD boundary.

9. The IC of claim 8 , wherein said field dielectric layer comprises a Local Oxidation of Silicon (LOCOS) oxide.

10. The IC of claim 8 , wherein said reduced doping finger edge region comprises a region counterdoped with a p-type dopant.

11. The IC of claim 8 , wherein said reduced doping finger edge region comprises a region lacking said nwell doping.

12. An integrated circuit, comprising:
a substrate;
a p-channel drain extended metal oxide semiconductor (DEPMOS) device at the substrate, the DEPMOS device having:
a doped surface layer in the substrate;
at least one nwell finger defining a nwell length direction and an nwell width direction, the nwell finger having a first n-type dopant concentration within the doped surface layer;
a first pwell on one side of the nwell finger including a p+ source therein and a second pwell on an opposite side of the nwell finger including a p+ drain;
a gate stack over the nwell finger between the source and the drain including a gate dielectric layer and a patterned gate electrode on the gate dielectric layer;
a field dielectric layer on a portion of the doped surface layer defining active area boundaries including a first active area having a first active area boundary along the nwell width direction,
wherein the nwell finger includes a finger edge region over a portion of the first active area boundary along the nwell width direction, the finger edge region having a net n-type dopant concentration less than the first n-type dopant concentration.

13. The integrated circuit of claim 12 , wherein the field dielectric layer comprises a Local Oxidation of Silicon (LOCOS) oxide.

14. The integrated circuit of claim 12 , wherein the finger edge region comprises a region counterdoped with a p-type dopant.

15. The integrated circuit of claim 12 , wherein the finger edge region comprises less n-type dopant than a region of the nwell finger with the first n-type dopant concentration.

16. The integrated circuit of claim 12 , wherein the finger edge region extends a total of between 1 μm and 4 μm in the nwell length direction, and is recessed from an edge of the nwell finger in the nwell width direction.

17. The integrated circuit of claim 12 , wherein the at least one nwell finger comprises a plurality of nwell fingers.

18. The integrated circuit of claim 12 , wherein said DEPMOS device has a symmetric drain structure.

Assignees

• Texas Instruments Inc

Inventors

• Tsai Chin-Yu
• Khan Imran
• Wu Xiaoju

Classifications

• H01L21/76224

  Electricity · mapped topic

• H01L29/7816 Primary

  Electricity · mapped topic

• H01L29/1087

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L29/66568

  Electricity · mapped topic