Array substrate manufacturing method and array substrate

Patent metadata

Field	Value
Publication number	US-10504946-B2
Application number	US-201816101534-A
Country	US
Kind code	B2
Filing date	Aug 13, 2018
Priority date	Feb 14, 2016
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

An array substrate manufacturing method and an array substrate are provided. The array substrate manufacturing method uses an organic photoresist material to form a passivation protection layer for substituting the conventional passivation protection layer that is made of a silicon nitride material and applies one mask to subject the passivation protection layer and a planarization layer to exposure and development so as to obtain a third via that is located above the first drain electrode and a fourth via that is located above the second drain electrode and, thus, compared to the prior art techniques, saves one mask and reduces one etching process so as to achieve the purposes of simplifying the manufacturing process and saving manufacturing cost. The array substrate so manufactured has a simple structure and a low manufacturing cost and possesses excellent electrical performance.

First claim

What is claimed is:

1. An array substrate, comprising a base plate, a light shielding layer located on the base plate, a buffer layer located on the light shielding layer and the base plate, a first poly silicon section and a second poly silicon section located on the buffer layer, a first gate insulation layer and a second gate insulation layer respectively located on middle areas of the first poly silicon section and the second poly silicon section, a first gate electrode and a second gate electrode respectively located on the first gate insulation layer and the second gate insulation layer and in alignment with the first and second gate insulation layers, an interlayer insulation layer located on the first gate electrode, the second gate electrode, the first poly silicon section, the second poly silicon section, and the buffer layer, a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode located on the interlayer insulation layer, a planarization layer located on the first source electrode, the first drain electrode, the second source electrode, the second drain electrode, and the interlayer insulation layer, a common electrode located on the planarization layer, a passivation protection layer located on the common electrode and the planarization layer, and a pixel electrode located on the passivation protection layer;
the first poly silicon section comprising a first channel zone corresponding to and located under the first gate insulation layer, N type heavy doping zones respectively located at two ends, and N type light doping zones respectively located between the N type heavy doping zones and the first channel zone; the second poly silicon section comprising a first channel zone corresponding to and located under the second gate insulation layer and P type heavy doping zones respectively located at two ends;
the interlayer insulation layer comprising first vias corresponding to and located above the N type heavy doping zones and second vias corresponding to and located above the P type heavy doping zones; the first source electrode and the first drain electrode being respectively connected, through the first vias, to the N type heavy doping zones; and the second source electrode and the second drain electrode being respectively connected, through the second vias, to the P type heavy doping zones;
the planarization layer and the passivation protection layer being both made of a material comprises an organic photoresist, the passivation protection layer and the planarization layer comprising, formed therein, a third via corresponding to and located above the first drain electrode and a fourth via corresponding to and located above the second drain electrode, the pixel electrode being electrically connected, through the third via and the fourth via, to the first drain electrode and the second drain electrode respectively.

2. The array substrate as claimed in claim 1 , wherein the passivation protection layer has a dielectric constant that is around 3-4; the base plate is a transparent plate; the first metal layer, the second metal layer, and the third metal layer are formed of a material comprising one of molybdenum, titanium, aluminum, and copper or a stacked combination of multiple ones thereof; the buffer layer, the first and second gate insulation layers, and the interlayer insulation layer are each a silicon oxide layer, a silicon nitride layer, or a composite layer of stacked silicon oxide layer and silicon nitride layer; and the first transparent conductive layer and the second transparent conductive layer are formed of a material comprises a metal oxide.

Assignees

• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Deng si

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/134309

  characterised by their geometrical arrangement · CPC title

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

• G02F2202/104

  poly-Si · CPC title