Method for fabricating damascene structure using fluorocarbon film

Patent metadata

Field	Value
Publication number	US-10504883-B2
Application number	US-201715720734-A
Country	US
Kind code	B2
Filing date	Sep 29, 2017
Priority date	Dec 15, 2016
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

A method for manufacturing an interconnect structure includes providing a metal interconnect layer, forming a dielectric layer on the metal interconnect layer, forming a fluorocarbon layer on the dielectric layer, forming a patterned hardmask layer on the fluorocarbon layer, etching the fluorocarbon layer and the dielectric layer using the patterned hardmask layer as a mask to form a trench in the dielectric layer and a through-hole through the dielectric layer to the metal interconnect layer, forming a metal layer filling the trench and the through-hole, and planarizing the metal layer until the planarized metal layer has an upper surface that is flush with an upper surface of the fluorocarbon layer. The interconnect structure thus formed has an improved reliability.

First claim

What is claimed is:

1. A method for manufacturing an interconnect structure, the method comprising:
providing a metal interconnect layer;
forming a dielectric layer on the metal interconnect layer;
forming a doped fluorocarbon layer on the dielectric layer;
forming a patterned hardmask layer on the doped fluorocarbon layer, wherein the patterned hardmask layer comprises:
a first hardmask layer comprising non-porous SiOCH on the doped fluorocarbon layer;
a second hardmask layer comprising TEOS on the first hardmask layer;
a third hardmask layer comprising TiN on the second hardmask layer;

etching the doped fluorocarbon layer and the dielectric layer using the patterned hardmask layer as a mask to form a trench in the dielectric layer and a through-hole through the dielectric layer to the metal interconnect layer;
forming a metal layer filling the trench and the through-hole; and
planarizing the metal layer until the planarized metal layer has an upper surface that is flush with an upper surface of the doped fluorocarbon layer.

2. The method of claim 1 , wherein the patterned hardmask layer comprises a first opening extending into the hardmask layer, and etching the doped fluorocarbon layer and the dielectric layer using the hardmask layer as the mask comprises:
forming a patterned first mask layer on the hardmask layer, the patterned first mask layer having a second opening extending to a bottom of the first opening;
etching the patterned hardmask layer, the doped fluorocarbon layer, and the dielectric layer using the first mask layer as a mask to form a third opening in the dielectric layer;
removing the first mask layer;
removing a portion of the dielectric layer below the third opening using the hardmask layer as a mask; and
removing a portion of the hardmask layer, a portion of the doped fluorocarbon layer, and a portion of the dielectric layer below the first opening to form the trench and the through-hole.

3. The method of claim 2 , wherein the first mask layer comprises two second openings each extending to the bottom of the first opening to form two through-holes extending to the metal interconnect layer.

4. The method of claim 2 , wherein forming the patterned hardmask layer on the doped fluorocarbon layer comprises:
forming a second mask layer on the third hardmask layer;
etching the third hardmask layer and the second hardmask layer using the second mask layer as a mask to form the first opening extending into the second hardmask layer or extending through the second hardmask layer to the first hardmask layer; and
removing the second mask layer.

5. The method of claim 4 , wherein forming the second mask layer on the third hardmask layer comprises:
forming a mask oxide layer on the third hardmask layer;
forming the second mask layer on the mask oxide layer; and
wherein etching the third hardmask layer and the second hardmask layer using the second mask layer as a mask comprises:
etching the mask oxide layer, the third hardmask layer, and the second hardmask layer using the second mask layer as a mask;
the method further comprising, after removing the second mask layer:
removing the mask oxide layer.

6. The method of claim 1 , further comprising, prior to forming the metal layer:
performing a heat treatment to remove moisture in the dielectric layer.

7. The method of claim 6 , wherein the heat treatment is performed at a temperature in a range between 100° C. and 400° C., and with at least one of nitrogen gas, ammonia gas, and hydrazine gas as a protective gas.

8. The method of claim 1 , further comprising:
forming a SiCN layer on the planarized metal layer and on the upper surface of the doped fluorocarbon layer.

9. The method of claim 1 , wherein the dielectric layer comprises a porous low-k dielectric layer.

10. The method of claim 1 , wherein the dielectric layer comprises a SiCN layer on the metal interconnect layer, a buffer layer on the SiCN layer, and a porous low-k dielectric layer on the buffer layer.

11. The method of claim 1 , wherein the doped fluorocarbon layer is a hydrogen-containing fluorocarbon layer.

12. The method of claim 1 , wherein the doped fluorocarbon layer has a thickness in a range between 5 angstroms and 1000 angstroms.

13. The method of claim 1 , wherein the doped fluorocarbon layer contains nitrogen.

14. The method of claim 1 , wherein the doped fluorocarbon layer contains boron.

Assignees

• Semiconductor Mfg Int Beijing Corp
• Semiconductor Mfg Int Shanghai Corp

Inventors

• Zhou Ming

Classifications

• H10P70/277

  the processing being a planarisation of conductive layers · CPC title

• H10P50/286

  of organic materials · CPC title

• H10P14/687

  the materials being fluorocarbon compounds, e.g. (CHxFy) n or polytetrafluoroethylene · CPC title

• H10W20/087

  involving multiple stacked pre-patterned masks · CPC title

• H10W20/074 Primary

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title