Chip-on-film package, display panel, and display device

Patent metadata

Field	Value
Publication number	US-10504830-B2
Application number	US-201715857744-A
Country	US
Kind code	B2
Filing date	Dec 29, 2017
Priority date	Feb 10, 2017
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

A chip-on-film package includes a base substrate on which a first pad region, a second pad region, and a third region located between the first pad region and the second pad region are defined, a dummy pad disposed on the first pad region, input pads disposed on the first pad region, output pads disposed on the second region, a first detection line disposed on the base substrate, and a second detection line disposed on the base substrate. The first detection line is connected to a first input pad and a second input pad via the second pad region to form a first loop between the first input pad and the second input pad, and the second detection line is connected to the dummy pad and the first detection line via the third region to form a second loop between the dummy pad and the first input pad.

First claim

What is claimed is:

1. A chip-on-film package comprising:
a base substrate on which a first pad region extends on a first side defining one side of the base substrate, a second pad region different from the first pad region extending on a second side opposite the first side defining an opposite side to the one side of the base substrate, and a third region located between the first pad region and the second pad region are defined;

a dummy pad disposed on the first pad region;
a plurality of input pads disposed on the first pad region;
a plurality of output pads disposed on the second pad region in a single row;
a first detection line disposed on the base substrate, wherein the first detection line includes a first sub-detection line connected between a first input pad of the input pads and a first output pad of the output pads and a second sub-detection line connected between a second input pad of the input pads and a second output pad of the output pads, the first sub detection line being connected to the second sub-detection line in the second pad region to form a first loop between the first input pad and the second input pad; and
a second detection line disposed on the base substrate, wherein the second detection line is connected between the dummy pad and the first detection line, the second detection line being connected to the first sub-detection line in the third region to form a second loop between the dummy pad and the first input pad.

2. The chip-on-film package of claim 1 , wherein the dummy pad comprises an alignment key for alignment of the input pads.

3. The chip-on-film package of claim 1 , wherein
the first sub-detection line is connected to the second sub-detection line through a short pad in the second pad region.

4. The chip-on-film package of claim 1 , wherein the second detection line comprises a detection pattern disposed on the third region in a zigzag pattern.

5. The chip-on-film package of claim 1 , wherein the dummy pad is located in outermost among the input pads and the dummy pad disposed on the first pad region.

6. The chip-on-film package of claim 1 , further comprising:
an integrated circuit chip connected to the dummy pad and the input pads,
wherein the integrated circuit chip calculates a first resistance value of the first loop and a second resistance value of the second loop and determines whether at least one of the second pad region and the third region is damaged based on the first resistance value and the second resistance value.

7. The chip-on-film package of claim 6 , wherein
the integrated circuit chip determines whether the second pad region and the third region are damaged based on an input pad resistance value of the input pads and the first resistance value,
the integrated circuit chip determines whether the third region is damaged based on the input pad resistance value and the second resistance value, and
the integrated circuit chip determines whether the second pad region is damaged based on a difference value between the first resistance value and the second resistance value.

8. A chip-on-film package comprising: a base substrate on which a first pad region extends on a first side defining one side of the base substrate, a second pad region different from the first pad region extending on a second side opposite the first side defining an opposite side to the one side of the base substrate, and a third region located between the first pad region and the second pad region are defined;
a dummy pad disposed on the first pad region;
a plurality of input pads disposed on the first pad region;
a plurality of output pads disposed on the second pad region in a single row;
a first detection line disposed on the base substrate, wherein the first detection line includes a first sub-detection line connected between a first input pad of the input pads and a first output pad of the output pads and a second sub-detection line connected between a second input pad of the input pads and a second output pad of the output pads, the first sub-detection line being connected to the second sub-detection line in the second pad region; and
a second detection line disposed on the base substrate, the second detection line is connected between the dummy pad and the first detection line in the third region.

9. The chip-on-film package of claim 8 , wherein
the first sub-detection line is connected to the second sub-detection line through a short pad in the second pad region.

10. The chip-on-film package of claim 8 , further comprising:
an inspection circuit is connected to the dummy pad and the input pads,
wherein the inspection circuit calculates a first resistance value between the first input pad and the second input pad and a second resistance value between the dummy pad and the first input pad, and the inspection circuit determines whether at least one of the second pad region and the third region is damaged based on the first resistance value and the second resistance value.

11. The chip-on-film package of claim 10 , wherein
the inspection circuit determines whether the second pad region and the third region are damaged based on an input pad resistance value of the input pads and the first resistance value,
the inspection circuit determines whether the third region is damaged based on the input pad resistance value and the second resistance value, and
the inspection circuit determines whether the second pad region is damaged based on a difference value between the first resistance value and the second resistance value.

Assignees

• Samsung Display Co Ltd

Inventors

• Lee Hee-Kwon
• Hong Seungkyun

Classifications

• H10W74/129

  forming a chip-scale package [CSP] · CPC title

• H10W70/688

  Flexible insulating substrates · CPC title

• H10W20/484

  Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes · CPC title

• H05K2201/10128

  Display · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title