Methods for forming through-substrate vias penetrating inter-layer dielectric

Patent metadata

Field	Value
Publication number	US-10504776-B2
Application number	US-201816047079-A
Country	US
Kind code	B2
Filing date	Jul 27, 2018
Priority date	Apr 27, 2012
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

A device includes a semiconductor substrate and a Metal-Oxide-Semiconductor (MOS) transistor. The MOS transistor includes a gate electrode over the semiconductor substrate, and a source/drain region on a side of the gate electrode. A source/drain contact plug includes a lower portion and an upper portion over the lower portion, wherein the source/drain contact plug is disposed over and electrically connected to the source/drain region. A gate contact plug is disposed over and electrically connected to the gate electrode, wherein a top surface of the gate contact plug is level with a top surface of the top portion of the source/drain contact plug. A Through-Substrate Via (TSV) extends into the semiconductor substrate. A top surface of the TSV is substantially level with an interface between the gate contact plug and the gate electrode.

First claim

What is claimed is:

1. A method comprising:
forming a transistor comprising:
a gate electrode over a semiconductor substrate; and
a source/drain region on a side of the gate electrode;

forming a first inter-layer dielectric to embed the gate electrode therein;
etching the first inter-layer dielectric and the semiconductor substrate to form an opening penetrating through the first inter-layer dielectric and extending into the semiconductor substrate;
filling the opening with a conductive material to form a through-via extending into the semiconductor substrate;
forming a second inter-layer dielectric over the first inter-layer dielectric;
forming a source/drain contact plug comprising a lower portion in the first inter-layer dielectric, and an upper portion over the lower portion and in the second inter-layer dielectric, wherein the source/drain contact plug is over and electrically connected to the source/drain region; and
forming a gate contact plug over and electrically connected to the gate electrode, wherein a top surface of the gate contact plug is level with a top surface of the upper portion of the source/drain contact plug, and wherein a top surface of the through-via is level with an interface between the gate contact plug and the gate electrode.

2. The method of claim 1 further comprising removing portions of the conductive material over the first inter-layer dielectric, wherein a remaining portion of the conductive material forms the through-via.

3. The method of claim 2 , wherein the removing the portions of the conductive material further comprises:
forming a polish stop layer over the first inter-layer dielectric;
polishing the conductive material, wherein the polish stop layer is used to stop the polishing; and
polishing the polish stop layer.

4. The method of claim 1 further comprising:
forming an etch stop layer over the first inter-layer dielectric, wherein a top surface of the through-via is in contact with the etch stop layer, and wherein the second inter-layer dielectric is formed over the etch stop layer.

5. The method of claim 4 , wherein the gate contact plug and the upper portion of the source/drain contact plug penetrate through the etch stop layer.

6. The method of claim 1 further comprising forming a via and a metal line using dual damascene processes, wherein a bottom surface of the via is in contact with a top surface of the gate contact plug.

7. The method of claim 1 , wherein the gate contact plug is wider than the gate electrode.

8. A method comprising:
forming an isolation region extending from a top surface of a semiconductor substrate into the semiconductor substrate;
forming a transistor comprising:
a source/drain region extending into the semiconductor substrate; and
a gate electrode over the semiconductor substrate;

forming a dielectric layer over the isolation region;
etching the dielectric layer, the isolation region, and the semiconductor substrate to form an opening;
filling a conductive material into the opening;
performing a backside grinding from a back surface of the semiconductor substrate to reveal the conductive material, wherein a remaining portion of the conductive material forms a through-via; and
forming a first contact plug and a second contact plug, both over and contacting a top surface of the through-via.

9. The method of claim 8 , wherein the filling the conductive material further comprises removing excess portions of the conductive material over the dielectric layer, wherein the gate electrode is exposed through the dielectric layer after the excess portions are removed.

10. The method of claim 8 further comprising forming a gate contact plug over and contacting the gate electrode, wherein the gate contact plug and the gate electrode form an interface, and the interface is substantially coplanar with a top surface of the through-via.

11. The method of claim 10 , wherein the gate contact plug is wider than the gate electrode.

12. The method of claim 8 further comprising;
forming a gate contact plug over and contacting the gate electrode; and
forming an etch stop layer over and contacting both the gate contact plug and the through-via.

13. The method of claim 12 , wherein the gate contact plug extends laterally beyond edges of the gate electrode.

14. The method of claim 8 further comprising forming a source/drain contact plug in the dielectric layer, wherein the source/drain contact plug has a top surface substantially coplanar with a top surface of the through-via.

15. A method comprising:
forming an isolation region extending from a top surface of a semiconductor substrate into the semiconductor substrate;
forming a transistor comprising:
a source/drain region extending into the semiconductor substrate; and
a gate electrode over the semiconductor substrate;

forming a first Inter-layer dielectric (ILD) over the isolation region, wherein the gate electrode is in the first ILD;
forming a Chemical Mechanical Polish (CMP) stop layer over the first ILD and the gate electrode;
forming an opening penetrating through the CMP stop layer, the first ILD, and the isolation region, wherein the opening extends into the semiconductor substrate;
filling the opening with a conductive material;
performing a first CMP to remove excess portions of the conductive material over the CMP stop layer; and
performing a second CMP to remove the CMP stop layer, wherein a remaining portion of the conductive material forms a through-via, wherein after the second CMP, the gate electrode is exposed.

16. The method of claim 15 further comprising grinding a back surface of the semiconductor substrate to reveal the conductive material.

17. The method of claim 15 further comprising forming a gate contact plug over and contacting the gate electrode.

18. The method of claim 17 further comprising:
forming a first etch stop layer over and contacting both the through-via and the gate electrode;
forming a second ILD over the first etch stop layer;
forming a contact plug over and contacting the through-via; and
forming a second etch stop layer over and contacting the gate contact plug and the contact plug.

19. The method of claim 15 , wherein after the second CMP, a top surface of a source/drain contact plug is exposed, and the source/drain contact plug is over and electrically connected to the source/drain region.

20. The method of claim 17 , wherein the gate contact plug is wider than the gate electrode.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Ming-Fa
• Wang Yu-Young
• Jan Sen-Bor

Classifications

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title