Systems for voltage regulation using signal buffers and related methods

Patent metadata

Field	Value
Publication number	US-10504564-B2
Application number	US-201816110936-A
Country	US
Kind code	B2
Filing date	Aug 23, 2018
Priority date	Sep 14, 2017
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

Voltage regulators and related methods are described. The voltage regulators described in the application may include an operational amplifier, an output transistor, and a signal buffer connected between the operational amplifier and the output transistor. In some embodiments, these voltage regulators are used in connection with memory units. A voltage regulator may be arranged such that the signal amplifier clamps the voltage at the gate of the output transistor to the output voltage when the memory unit is in an idle mode. In this way, when the memory is accessed, the amplitude and duration of output voltage overshoots can be limited, relative to some voltage regulators.

First claim

What is claimed is:

1. An electronic system comprising:
a memory unit;
a voltage regulator comprising:
an operational amplifier having an output terminal;
a signal buffer coupled to the output terminal of the operational amplifier, the signal buffer having at least first and second terminals; and
an output transistor having an input terminal, and an output terminal coupled to the memory unit, the input terminal of the output transistor being coupled to the first terminal of the signal buffer and the output terminal of the output transistor being coupled to the second terminal of the signal buffer,
wherein the signal buffer is configured to set a voltage at the input terminal of the output transistor to be substantially equal to a voltage at the output terminal of the output transistor in response to an overshoot in the voltage at the output terminal of the output transistor.

2. The electronic system of claim 1 , wherein the operational amplifier has an input terminal coupled, through a resistive element, to the output terminal of the output transistor.

3. The electronic system of claim 1 , wherein the signal buffer exhibits a voltage gain that is less than 1.

4. A voltage regulator comprising:
an operational amplifier having an output terminal;
a signal buffer coupled to the output terminal of the operational amplifier, the signal buffer having at least first and second terminals; and
an output transistor having an input terminal and an output terminal, the input terminal of the output transistor being coupled to the first terminal of the signal buffer and the output terminal of the output transistor being coupled to the second terminal of the signal buffer,
wherein the signal buffer is configured to set a voltage at the input terminal of the output transistor to be substantially equal to a voltage at the output terminal of the output transistor in response to an overshoot in the voltage at the output terminal of the output transistor.

5. The voltage regulator of claim 4 , wherein the operational amplifier has an input terminal coupled, through a resistive element, to the output terminal of the output transistor.

6. The voltage regulator of claim 4 , wherein the signal buffer exhibits a voltage gain that is less than 1.

7. The voltage regulator of claim 4 , wherein the signal buffer comprises a current mirror.

8. The voltage regulator of claim 7 , wherein a first terminal of the current mirror is coupled to the output terminal of the operational amplifier and a second terminal of the current mirror is coupled to the output terminal of the output transistor.

9. The voltage regulator of claim 8 , wherein the second terminal of the current mirror is coupled to the output terminal of the output transistor through a transistor.

10. The voltage regulator of claim 4 , wherein the output terminal of the output transistor is coupled to a memory unit.

11. The voltage regulator of claim 4 , wherein the input terminal of the output transistor is a gate terminal and the output terminal of the output transistor is a source or emitter terminal.

12. The voltage regulator of claim 4 , wherein neither the first terminal of the signal buffer nor the second terminal of the signal buffer is coupled to ground.

13. The voltage regulator of claim 4 , wherein the output transistor is a MOSFET.

14. The voltage regulator of claim 13 , wherein the MOSFET is arranged in a common-drain or common-collector configuration.

15. A method for regulating an output voltage provided to a load, the method comprising:
when the load is accessed, providing the output voltage to the load with a voltage regulator comprising a signal buffer and an output transistor; and
when the load is in an idle mode, regulating the output voltage by clamping, with the signal buffer, a voltage at a gate terminal of the output transistor to the output voltage
wherein clamping the voltage at the gate terminal of the output transistor to the output voltage comprises causing the voltage at the gate terminal of the output transistor to be substantially equal to the output voltage.

16. The method of claim 15 , wherein:
when accessed, the load draws a first current value from the voltage regulator; and
when in the idle mode, the load draws a second current value from the voltage regulator, the first current value being greater, in absolute value, than the second current value.

17. The method of claim 15 , wherein the load comprises a memory unit, and wherein, when the load is accessed, a read and/or write operation is performed on the memory unit.

Assignees

• Mediatek Inc

Inventors

• Chen Wei-Chung
• Huang Tzu-Chi
• Hsu Kuo-Chun

Classifications

• G05F1/59

  including plural semiconductor devices as final control devices for a single load · CPC title

• G05F1/575

  characterised by the feedback circuit · CPC title

• G11C5/147 Primary

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• H03F3/505

  with field-effect devices · CPC title

• G05F1/56 Primary

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title