DIMM SSD Addressing performance techniques

Patent metadata

Field	Value
Publication number	US-10503657-B2
Application number	US-201815953397-A
Country	US
Kind code	B2
Filing date	Apr 13, 2018
Priority date	Oct 7, 2015
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

A Non-Volatile Dual In-Line Memory Module is disclosed (NVDIMM). The NVDIMM may be installed in a Dual In-Line Memory Module (DIMM) docket. The NVDIMM may include a non-volatile memory. A device driver may intercept a request for a memory address destined for a host memory controller, replace the memory address with a pre-mapped memory address or an alias of the pre-mapped memory address, and send the pre-mapped memory address to the host memory controller, so that the host memory controller generates a target memory address to NVDIMM.

First claim

What is claimed is:

1. A device, comprising:
a Non-Volatile Dual In-Line Memory Module (NVDIMM) installed in a Dual In-Line Memory Module (DIMM) socket, the NVDIMM including a memory and an exposed memory, the exposed memory including a first size of the exposed memory and a base address of the exposed memory; and
a device driver operating on a host processor, the device driver operative to intercept a memory address destined for a host memory controller and replace the memory address with an intermediate address in a request sent to the host memory controller, the intermediate address different from the memory address and generated using a physical-to-intermediate mapping on the memory address,
wherein the exposed memory includes a directly addressable memory and the memory address is in the exposed memory.

2. A device according to claim 1 , wherein the intermediate address is designed such that the host memory controller transmits a target memory address to the NVDIMM responsive to the intermediate address, the target memory address including a physical location of a value stored at the memory address.

3. A device according to claim 2 , wherein the device driver is operative to generate the intermediate address from the memory address responsive to the first size of the exposed memory in the NVDIMM, the base address of the exposed memory in the NVDIMM, a second size of a logical segment of the exposed memory in the NVDIMM, and a memory controller operating mode of the host memory controller.

4. A device according to claim 3 , wherein the device driver is further operative to generate the intermediate address from the memory address using the physical-to-intermediate mapping responsive to a logical-to-physical mapping of the memory address by the host memory controller.

5. A method, comprising:
receiving a request to access a memory address of a Non-Volatile Dual In-Line Memory Module (NVDIMM), the NVDIMM including a memory and an exposed memory, the exposed memory including a first size of the exposed memory and a base address of the exposed memory the memory address in the exposed memory;
pre-mapping the memory address to an intermediate address using a physical-to-intermediate transformation, the intermediate address different from the memory address responsive to a first size of an exposed memory in the NVDIMM, and a base address of the exposed memory in the NVDIMM, a second size of a logical segment of the exposed memory in the NVDIMM, a memory controller operating mode of the host memory controller, and a logical-to-physical transformation used by the host memory controller; and
sending the intermediate address to a host memory controller,
wherein the host memory controller sends a target memory address to the NVDIMM, the target memory address responsive to the intermediate address and representing a physical location of a value stored at the memory address, and
wherein the exposed memory includes a directly addressable memory.

6. An article, comprising a non-transitory storage medium, the tangible storage medium having stored thereon instructions that, when executed by a machine, result in:
receiving a request to access a memory address of a Non-Volatile Dual In-Line Memory Module (NVDIMM), the NVDIMM including a memory and an exposed memory, the exposed memory including a first size of the exposed memory and a base address of the exposed memory, the memory address in the exposed memory;
pre-mapping the memory address to an intermediate address using a physical-to-intermediate transformation, the intermediate address different from the memory address responsive to a first size of an exposed memory in the NVDIMM, and a base address of the exposed memory in the NVDIMM, a second size of a logical segment of the exposed memory in the NVDIMM, a memory controller operating mode of the host memory controller, and a logical-to-physical transformation used by the host memory controller; and
sending the intermediate address to a host memory controller,
wherein the host memory controller sends a target memory address to the NVDIMM, the target memory address responsive to the intermediate address and including a physical location of a value stored at the memory address, and
wherein the exposed memory includes a directly addressable memory.

7. A device according to claim 1 , wherein the host memory controller implements a logical-to-physical mapping on the intermediate address.

8. A method according to claim 5 , wherein the host memory controller implements a logical-to-physical mapping on the intermediate address.

9. An article according to claim 6 , wherein the host memory controller implements a logical-to-physical mapping on the intermediate address.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hanson Craig
• Swarbrick Ian
• Bekerman Michael
• CHANG Chihjen

Classifications

• G06F2212/657

  Virtual address space management · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F2212/1004

  Compatibility, e.g. with legacy hardware · CPC title

• G06F12/10 Primary

  Address translation · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title