Thread importance based processor core parking and frequency selection

Patent metadata

Field	Value
Publication number	US-10503238-B2
Application number	US-201715608712-A
Country	US
Kind code	B2
Filing date	May 30, 2017
Priority date	Nov 1, 2016
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

Each processor core in a computing device supports various different frequency ranges, also referred to as p-states, and can operate to run threads at any one of those different frequency ranges. Threads in the computing device are assigned one of multiple importance levels. A processor core is configured to run at a particular frequency range or in accordance with a particular energy performance preference based on the importance level of the thread it is running. A utilization factor of a processor core can also be determined over some time duration, the utilization factor being based on the amount of time during the time duration that the processor core was running a thread(s), and also based on the importance levels of the thread(s) run during the time duration. The utilization factor can then be used to determine whether to park the processor core.

First claim

What is claimed is:

1. A method comprising:
executing a workload of a processor core at each of respective different frequencies among frequencies at which the processor core can run;
programmatically determining, based on the executing, efficiencies of the processor core at each of the respective different frequencies, each efficiency corresponding to a respective ratio between frequency and power consumption;
determining frequency ranges based on the determined efficiencies, and associating the frequency ranges with importance levels, respectively, wherein each frequency range comprises corresponding upper and lower frequencies within which the processor core is allowed to run to execute a thread;
determining an importance level of a first thread scheduled to run on the processor core, the importance level being one of the importance levels;
selecting, from among the determined frequency ranges, a frequency range associated with the determined importance level;
configuring the processor core to run at the selected frequency range while running the first thread; and
wherein the importance levels include a first importance level and a second importance level that is lower than the first importance level, and wherein determining the frequency ranges based on the determined efficiencies is such that operation of the processor core in a frequency range associated with the second importance level is more efficient than operation of the processor core in a frequency range associated with the first importance level.

2. The method as recited in claim 1 , each frequency range having been determined based on efficiency of the processor core at each of multiple different frequencies at which the processor core can run.

3. The method as recited in claim 1 , the importance levels respectively comprising two or more quality of service levels.

4. The method as recited in claim 1 , the configuring the processor core comprising writing an indication of the selected frequency range to one or more registers of the processor core.

5. The method as recited in claim 1 , the configuring the processor core further comprising including an indication of the importance level in context information provided to the processor core when the processor core switches contexts to run the first thread.

6. The method as recited in claim 1 , the selecting a frequency range further comprising determining an energy performance preference value, the energy performance preference value indicating to the processor core whether to prefer high performance or lower energy usage while running the first thread.

7. The method as recited in claim 1 , further comprising:
determining a utilization factor of the processor core based at least in part on the importance levels of threads run on the processor core over a given time duration; and
determining, based on the utilization factor of the processor core, whether to park the processor core.

8. A computing device comprising:
a processor core;
storage hardware storing associations of different frequency ranges with different importance levels for threads, where the different frequency ranges are determined based on efficiencies of the processor core at each of respective different frequencies at which the processor core can run, each efficiency corresponding to a respective ratio between frequency and power consumption;
a thread importance determination module configured to determine an importance level of a first thread scheduled to run on the processor core, the importance level being one of multiple different importance levels that threads running on the processor core can have; and
a core frequency configuration module configured to
select a frequency range associated with the importance level from among the different frequency ranges, wherein each frequency range comprises corresponding upper and lower frequencies within which the processor core is allowed to run to execute a thread; and to
configure the processor core to run at the frequency range while running the first thread;

wherein the importance levels include a first importance level and a second importance level that is lower than the first importance level, and wherein the frequency ranges are determined based on the efficiencies such that operation of the processor core in a frequency range associated with the second importance level is more efficient than operation of the processor core in a frequency range associated with the first importance level.

9. The computing device as recited in claim 8 , the core frequency configuration module being further configured to determine the frequency range associated with the importance level for the first thread, each frequency range having been determined based on efficiency of the processor core at each of multiple different frequencies at which the processor core can run.

10. The computing device as recited in claim 8 , the core frequency configuration module being further configured to select the frequency range associated with the importance level for the first thread based on an energy performance preference value, the energy performance preference value indicating to the processor core whether to prefer high performance or lower energy usage while running the first thread.

11. The computing device as recited in claim 8 , further comprising a core parking module configured to determine a utilization factor of the processor core based at least in part on the importance levels of multiple threads run on the processor core over a given time duration, and to determine, based on the utilization factor of the processor core, whether to park the processor core.

12. The computing device as recited in claim 11 , the core parking module being further configured to determine the utilization factor by excluding from consideration in determining the utilization factor one or more of the multiple threads having less than a threshold importance level.

13. The computing device as recited in claim 11 , the determining the utilization factor comprising weighting, for each of the threads run on the processor core over the given time duration, the thread based on the importance level of the thread.

14. Computer-readable storage media storing information configured to cause a computing device to perform a process, the process comprising:
executing a workload of a processor core at each of respective different frequencies among frequencies at which the processor core can run;
programmatically determining, based on the executing, efficiencies of the processor core at each of the respective different frequencies, each efficiency corresponding to a respective ratio between frequency and power consumption;
determining frequency ranges based on the determined efficiencies, and associating the frequency ranges with importance levels, respectively, wherein each frequency range comprises corresponding upper and lower frequencies within which the processor core is allowed to run to execute a thread;
determining an importance level of a first thread scheduled to run on the processor core, the importance level being one of the importance levels;
selecting, from among the determined frequency ranges, a frequency range associated with the determined importance level;
configuring the processor core to run at the selected frequency range while running the first thread; and
wherein the importance levels include a first importance level and a second importance level that is lower than the first importance level, and wherein determining the frequency ranges based on the determined efficiencies is such that operation of the processor core in a freque

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Iyigun Mehmet
• Hsu Kai-Lun
• Nair Rahul
• Bellon Mark Allan
• Kishan Arun U
• Brown Tristan A

Classifications

• G06F1/3243 Primary

  Power saving in microcontroller unit · CPC title

• G06F9/5044

  considering hardware capabilities · CPC title

• G06F9/5094

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F9/226

  Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title