Solid state imaging apparatus including photodetecting section

Patent metadata

Field	Value
Publication number	US-10498995-B2
Application number	US-201715795470-A
Country	US
Kind code	B2
Filing date	Oct 27, 2017
Priority date	Jun 7, 2013
Publication date	Dec 3, 2019
Grant date	Dec 3, 2019

Abstract

A solid-state imaging device includes a photodetecting section, a vertical shift register section, first row selection lines, and second row selection lines. The vertical shift register section provides the row selection lines of the m-th row with common row selection signals.

First claim

The invention claimed is:

1. A solid-state imaging device comprising:
a photodetecting section having M×N pixels (each of M and N being an integer of 2 or more), each pixel including one photodiode and first and second switch circuits, each switch circuit having a first terminal connected to the one photodiode, two-dimensionally arrayed in M rows and N columns, and each switch circuit also having a second terminal and a control terminal;
N readout lines provided for the respective columns and connected to the second terminals of the first and second switch circuits included in the pixels of the corresponding columns;
M first row selection lines provided for the respective rows and connected to the control terminals of the first switch circuits included in the pixels of the corresponding rows;
M second row selection lines provided for the respective rows and connected to the control terminals of the second switch circuits included in the pixels of the corresponding rows, wherein the first row selection lines are separate and distinct from the second row selection lines; and
a shift register section for generating a row selection signal for controlling an open/closed state of the first and second switch circuits for each row and providing the first and second row selection lines with the row selection signal.

2. The solid-state imaging device according to claim 1 , wherein the first and second row selection lines are disposed in a region between the pixels.

3. The solid-state imaging device according to claim 1 , wherein one row selection line of the first and second row selection lines is disposed in a region between the pixels, and the other row selection line is disposed on the pixel.

4. The solid-state imaging device according to claim 3 , further comprising a reference potential line disposed between the other row selection line and the pixel.

5. The solid-state imaging device according to claim 1 , wherein the first and second switch circuits in each of the pixels are juxtaposed with each other in the column direction.

6. The solid-state imaging device according to claim 1 , further comprising:
first buffers having respective output terminals connected to the first row selection lines; and
second buffers having respective output terminals connected to the second row selection lines, wherein
the shift register section has signal output terminals provided two by two for the respective rows for outputting the row selection signal, in each row, one signal output terminal of the two signal output terminals being connected to the input terminal of the first buffer, and the other signal output terminal being connected to the input terminal of the second buffer.

7. The solid-state imaging device according to claim 1 , further comprising:
buffers having respective output terminals connected to both the first row selection lines and the second row selection lines, wherein
the shift register section has signal output terminals provided one by one for the respective rows for outputting the row selection signal, the signal output terminals being connected to the input terminals of the buffers of the corresponding rows.

8. The solid-state imaging device according to claim 1 , wherein, in at least part of the rows, the row selection signals are input to the first and second row selection lines for the same row at the same timing.

9. The solid-state imaging device according to claim 1 , wherein the shift register section includes M shift register circuits, and the M shift register circuits are connected in series.

Assignees

• Hamamatsu Photonics Kk

Inventors

• Fujita Kazuki
• Kyushima Ryuji
• Sawada Junichi
• Mori Harumichi

Classifications

• H04N25/778 Primary

  comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself · CPC title

• H04N25/767

  Horizontal readout lines, multiplexers or registers · CPC title

• H04N25/68

  applied to defects · CPC title

• H04N5/367

  Electricity · mapped topic

• H04N5/37457

  Electricity · mapped topic