Voltage-to-current transconductance operational amplifier with adaptive biasing

Patent metadata

Field	Value
Publication number	US-10498300-B2
Application number	US-201715651733-A
Country	US
Kind code	B2
Filing date	Jul 17, 2017
Priority date	Jul 17, 2017
Publication date	Dec 3, 2019
Grant date	Dec 3, 2019

Abstract

An IC for power conversion includes bias circuitry that generates one or more bias voltages. An adaptive biasing circuit adaptively shifts an input signal having a negative value to a positive value. An operational transconductance amplifier (OTA) receives a supply bias current and the first and second bias voltages. The OTA has first and second input terminals coupled to the input signal and ground, respectively. The OTA has first and second transistors coupled to the first and second input terminals through first and second resistors at first and second internal nodes, respectively. Additional circuitry of the OTA is coupled to the second internal node. The additional circuitry insures that the voltage at the second internal node follows the voltage at the first internal node. The OTA generates an output current signal responsive to a differential input voltage applied across the first and second input terminals.

First claim

I claim:

1. An integrated circuit (IC) for voltage-to-current conversion comprising:
bias circuitry coupled to receive one or more input bias voltages referenced to ground, the bias circuitry generating one or more bias voltages;
an adaptive biasing circuit coupled to receive the one or more input bias voltages and the one or more bias voltages, the adaptive biasing circuit being configured to adaptively shift an input signal having a negative value to a positive value above ground; and
an operational transconductance amplifier (OTA) coupled to receive a supply bias current and the one or more bias voltages, the OTA having first and second input terminals coupled to the input signal and ground, respectively, the OTA having first and second transistors coupled to the first and second input terminals through first and second resistors at first and second internal nodes, respectively, in operation, the supply bias current flows through each of the first and second transistors, the OTA further including additional circuitry coupled to the second internal node, the additional circuitry being configured to insure that the voltage at the second internal node follows the voltage at the first internal node, the OTA generating an output current signal responsive to a differential input voltage applied across the first and second input terminals.

2. The IC of claim 1 wherein the output current signal is linearly related with the input signal.

3. The IC of claim 1 further comprising a third resistor coupled between the first input terminal and ground, the third resistor having a relatively low resistance value as compared to the first and second resistors.

4. The IC of claim 1 wherein the first and second resistors each have a substantially equal resistance value.

5. The IC of claim 1 wherein the bias circuitry includes first and second switching legs each carrying a substantially equal current in operation, each of the first and second switching legs including high-side cascode structure PMOS transistors coupled in series with low-side cascode structure NMOS transistors, the one or more input bias voltages being coupled to the gates of cascode structure NMOS transistors, and the one or more bias voltages being coupled to the gates of cascode structure PMOS transistors of the first and second switching legs.

6. The IC of claim 5 wherein during operation a voltage drop across the first resistor level shifts the input signal such that sources of the first and second transistors stay above a minimum threshold.

7. The IC of claim 1 wherein the first and second transistors comprise NMOS transistors.

8. The IC of claim 1 wherein the additional circuitry comprises third and fourth transistors, the third transistor being coupled to the second internal node, during operation the third transistor providing current flow through the second resistor, the fourth transistor being coupled between the second internal node and ground, the supply bias current flowing through the fourth transistor.

9. The IC of claim 8 wherein the third transistor comprises a PMOS transistor and the fourth transistor comprises a NMOS transistor.

10. An integrated circuit (IC) or converting a differential input voltage into an output current comprising:
bias circuitry comprising first and second switching legs, each including high-side transistors coupled in series with low-side transistors, the low-side transistors coupled to receive one or more input bias voltages, the high-side transistors generating one or more bias voltages;
adaptive biasing circuitry configured to adaptively shift an input voltage signal having a negative value to a positive value above ground; and
an operational transconductance amplifier (OTA) having a cascode-pair of PMOS transistors coupled to receive the one or more bias voltages, the OTA having first and second input terminals coupled to the input voltage signal and ground, respectively, a difference between the input voltage signal and ground comprising the differential input voltage, the OTA having first and second NMOS transistors coupled to the first and second input terminals through first and second resistors at first and second internal nodes, respectively, in operation, a supply bias current flowing through each of the first and second transistors and through the cascode-pair of PMOS transistors, the OTA being configured to insure that the voltage at the second internal node follows the voltage at the first internal node, the OTA generating an output current signal responsive to a differential input voltage applied across the first and second input terminals.

11. The IC of claim 10 wherein the input voltage signal has a range that extends between positive and negative values.

12. The IC of claim 10 wherein the OTA has an input impedance to ground that is substantially lower than the input impedance to a supply.

13. The IC of claim 10 wherein the high-side transistors and the low-side transistors of the bias circuitry are each configured as a cascode-pair.

14. The IC of claim 10 wherein the first input terminal is coupled to ground through an input resistor having a substantially lower resistance value as compared to the first resistor.

15. The IC of claim 10 where the first and second resistors each have a substantially equal resistance value.

16. The IC of claim 10 wherein the OTA further includes third and fourth transistors, the third transistor being coupled to the second internal node, during operation the third transistor providing current flow through the second resistor, the fourth transistor being coupled between the second internal node and ground, the supply bias current flowing through the fourth transistor.

17. The IC of claim 16 wherein the third transistor is a PMOS transistor and the fourth transistor is a NMOS transistor.

18. The IC of claim 17 herein the third transistor is coupled to a supply bus through a diode.

19. The IC of claim 10 wherein the output current signal has a scaled linear relationship with the input voltage signal.

Assignees

• Power Integrations Inc

Inventors

• Schulz Frank Joseph

Classifications

• H03G2201/40

  Combined gain and bias control · CPC title

• H03F3/45273

  Mirror types · CPC title

• H03G3/3042

  in modulators, frequency-changers, transmitters or power amplifiers · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03G5/22

  having semiconductor devices · CPC title