Electronic device

Patent metadata

Field	Value
Publication number	US-10497789-B2
Application number	US-201815936513-A
Country	US
Kind code	B2
Filing date	Mar 27, 2018
Priority date	Dec 8, 2013
Publication date	Dec 3, 2019
Grant date	Dec 3, 2019

Abstract

A transistor structure is configured as a vertical type transistor. The transistor structure has a patterned electrode located between a gate electrode and a channel region of the transistor structure. The patterned electrode has one or more regions of discontinuity of the electrode. The patterned source electrode has at least two layers having at least a first and second barriers for injection of charge carriers into the channel region. The patterned electrode is configured such that a second layer having a second, higher, barrier for injection of charge carriers is configured to provide a physical barrier for flow of charge carriers from the electrode into the channel region.

First claim

The invention claimed is:

1. A transistor structure configured as a vertical type transistor and comprising a patterned electrode located between a gate electrode and a channel region of the transistor structure, the patterned electrode comprises one or more regions of discontinuity of said electrode, said patterned source electrode comprises at least first and second layers having at least first and second charge injection properties respectively for injection of charge carriers into the channel region,
the patterned electrode is configured such that the second layer has a higher barrier for injection of charge carriers as compared to charge injection properties of the first layer;
wherein said one or more regions of discontinuity of said patterned electrode are configured such that the second layer of the patterned electrode skirts over edges of the first layer of said patterned electrode at edges of said regions of discontinuity.

2. The transistor structure of claim 1 , wherein said patterned electrode is a source electrode of the transistor structure.

3. The transistor structure of claim 1 , wherein said patterned electrode is configured as a two layered electrode.

4. The transistor structure of claim 1 , wherein said patterned electrode is configured as a multi layered electrode, comprising at least two layers of conducting materials.

5. The transistor structure of claim 1 , wherein said one or more regions of discontinuity of the patterned electrode are regions of discontinuity in electrical conductivity along said patterned electrode.

6. The transistor structure of claim 1 , wherein said one or more regions of discontinuity of the patterned electrode being configured as one or more holes along surface of the electrodes, thereby allowing penetration of electric field generated by the gate electrode into the channel region.

7. The transistor structure of claim 1 , wherein at least one of the first and second layers is configured as a multi-layered structure, said multi layered structure comprising at least two of a conducting layer, a semiconducting layer, and an insulating layer.

8. The transistor structure of claim 1 , wherein at least one region of the second layer of the patterned electrode covers the first layer.

9. The transistor structure of claim 1 , wherein the patterned electrode is configured to have at least one of the following configurations: step-source edge geometry, tilted edge geometry and curved edge geometry in at least one of said one or more regions of discontinuity.

10. The transistor structure of claim 1 , wherein the first layer comprises a conducting material selected from: Li, Ca, Mg, Al, Ag, ZnO, Au, and the second layer comprises a conductive material selected from: Al, Ag, Au, MoO 3 , Pt and Se.

11. The transistor structure of claim 1 , wherein the first layer comprises a conducting material selected from: Al, Ag, Au, MoO 3 , Pt, Se, and the second layer comprises a conductive material selected from: Li, Ca, Mg, Al, Ag, ZnO and Au.

12. The transistor structure of claim 1 , wherein the first and second layers of said patterned electrode are configured with electronically conductive materials having selected first and second charge injection properties.

Assignees

• Technion Res & Dev Foundation

Inventors

• Tessler Nir
• Ben Sasson Ariel Jacques
• Greenman Michael

Classifications

• H01L29/7827

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic

• H01L51/105

  Electricity · mapped topic

• H01L51/057

  Electricity · mapped topic

• H01L29/41741 Primary

  Electricity · mapped topic