Capacitor structures, decoupling structures and semiconductor devices including the same

Patent metadata

Field	Value
Publication number	US-10497775-B2
Application number	US-201916268185-A
Country	US
Kind code	B2
Filing date	Feb 5, 2019
Priority date	Sep 5, 2014
Publication date	Dec 3, 2019
Grant date	Dec 3, 2019

Abstract

Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a decoupling structure comprising a first capacitor and a second capacitor that is different from the first capacitor, the decoupling structure comprising:
a first plurality of conductive patterns that each extend in a vertical direction;
a first conductive plate commonly connected to the first plurality of conductive patterns;
a second plurality of conductive patterns that each extend in the vertical direction;
a second conductive plate commonly connected to the second plurality of conductive patterns;
a horizontally disposed unitary supporting structure that structurally supports the first plurality of conductive patterns and the second plurality of conductive patterns;
a common electrode disposed between ones of the first plurality of conductive patterns and between ones of the second plurality of conductive patterns;
a lower insulating layer below the first plurality of conductive patterns and the second plurality of conductive patterns; and
a lower conductive plate spaced apart from the first and second conductive plate with the lower insulating layer therebetween,
wherein the first plurality of conductive patterns and the common electrode comprise electrodes of the first capacitor, and the second plurality of conductive patterns and the common electrode comprise electrodes of the second capacitor, and
wherein the first plurality of conductive patterns and the second plurality of conductive patterns are horizontally spaced apart from each other in a first direction with a separation region therebetween.

2. The integrated circuit device of claim 1 , wherein:
a first portion of the common electrode overlies an upper surface of the unitary supporting structure; and
an upper surface of the first portion of the common electrode is disposed at a level higher than an upper surface of each of the first plurality of conductive patterns.

3. The integrated circuit device of claim 2 , wherein the upper surface of the unitary supporting structure is disposed at a level higher than the upper surface of the each of the first plurality of conductive patterns.

4. The integrated circuit device of claim 1 , further comprising a substrate underneath the decoupling structure,
wherein the first conductive plate and the second conductive plate are horizontally spaced apart from each other with a space therebetween, and the space is disposed between the first plurality of conductive patterns and the second plurality of conductive patterns.

5. The integrated circuit device of claim 4 , further comprising an insulating pattern between the first and second conductive plates and the common electrode,
wherein the insulating pattern comprises an upper portion and a lower portion that protrudes toward the substrate in the space between the first conductive plate and the second conductive plate.

6. The integrated circuit device of claim 4 , wherein the space between the first conductive plate and the second conductive plate comprises a first space,
wherein the integrated circuit device further comprises a third conductive plate and a fourth conductive plate between the first and second of conductive plates and the substrate, and
wherein:
the third conductive plate and the fourth conductive plate are horizontally spaced apart from each other with a second space therebetween;
the second space is disposed between the first plurality of conductive patterns and the second plurality of conductive patterns; and
the first conductive plate and the third conductive plate comprise electrodes of a third capacitor, and the second conductive plate and the fourth conductive plate comprise electrodes of a fourth capacitor that is different from the third capacitor.

7. The integrated circuit device of claim 1 , wherein each of the first plurality of conductive patterns has a height at least 20 times greater than a width of the each of the first plurality of conductive patterns.

8. A decoupling structure comprising:
a plurality of vertically disposed electrode patterns on a substrate, the plurality of electrode patterns comprising:
a plurality of first electrode patterns disposed along a first horizontal direction at a first interval;
a plurality of second electrode patterns disposed along the first horizontal direction at a second interval, wherein the plurality of first electrode patterns and the plurality of second electrode patterns are spaced apart from each other in the first horizontal direction with a separation region therebetween, and the separation region has a width in the first horizontal direction greater than the first interval or the second interval; and
a common electrode disposed between ones of the plurality of first electrode patterns and between ones of the plurality of second electrode patterns,
wherein the plurality of first electrode patterns and the plurality of second electrode patterns are not disposed in the separation region.

9. The decoupling structure of claim 8 , further comprising a unitary supporting structure at least partially surrounding respective sidewalls of the plurality of first electrode patterns and respective sidewalls of the plurality of second electrode patterns,
wherein the unitary supporting structure comprises a plurality of openings, and
wherein the unitary supporting structure extends across the separation region.

10. The decoupling structure of claim 8 , wherein the first interval and the second interval are substantially equal.

11. The decoupling structure of claim 8 , wherein the decoupling structure further comprises a first capacitor and a second capacitor that is different from the first capacitor,
wherein the plurality of first electrode patterns collectively comprise a first electrode of the first capacitor, and the common electrode comprises a second electrode of the first capacitor, and
wherein the plurality of second electrode patterns collectively comprise a first electrode of the second capacitor, and the common electrode comprises a second electrode of the second capacitor.

12. The decoupling structure of claim 11 , further comprising a pair of conductive plates underneath the plurality of electrode patterns,
wherein the pair of conductive plates comprises a first conductive plate that is electrically connected to the plurality of first electrode patterns and a second conductive plate that is electrically connected to the plurality of second electrode patterns.

13. The decoupling structure of claim 8 , wherein the plurality of first electrode patterns and the plurality of second electrode patterns are not disposed in the separation region.

14. An integrated circuit device comprising:
a decoupling structure comprising a first capacitor and a second capacitor that is different from the first capacitor, the decoupling structure comprising:
a first conductive plate;
a first plurality of conductive patterns connected to the first conductive plate;
a second conductive plate;
a second plurality of conductive patterns connected to the second conductive plate;
an insulating layer between the first conductive plate and the second conductive plate; and
a common electrode disposed between ones of the first plurality of conductive patterns and between ones of the second plurality of conductive patterns,
wherein the first plurality of conductive patterns and the common electrode comprise electrodes of the first capacitor, and the second plurality of conductive patterns and the common electrode comprise electrodes of the second capacitor,
wherein the first plurality of conductive patterns and the second plurality of

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jong-Min
• Jun Jongryul
• Kim Eun A
• Lim Jung-Bum

Classifications

• H01L28/82

  Electricity · mapped topic

• H01L27/0805

  Electricity · mapped topic

• H01L28/86

  Electricity · mapped topic

• H01L28/92

  Electricity · mapped topic

• H01L28/90 Primary

  Electricity · mapped topic