Display apparatus and electroluminescence display

Patent metadata

Field	Value
Publication number	US-10497760-B2
Application number	US-201816164516-A
Country	US
Kind code	B2
Filing date	Oct 18, 2018
Priority date	Dec 27, 2017
Publication date	Dec 3, 2019
Grant date	Dec 3, 2019

Abstract

Disclosed is a display apparatus that may include a substrate including a display area and a non-display area adjacent to the display area, a thin film transistor disposed in the display area, an integrated driver disposed in the non-display area and electrically connected with the thin film transistor, a plurality of test lines connected with the integrated driver and spaced apart from each other, and an opening portion configured to expose an upper surface of the substrate and obtained by removing a plurality of inorganic insulating layers disposed in the area between the plurality of test lines.

First claim

What is claimed is:

1. A display apparatus comprising:
a substrate including a display area and a non-display area adjacent to the display area;
a thin film transistor disposed in the display area;
an integrated driver disposed in the non-display area and electrically connected with the thin film transistor;
a plurality of test lines connected with the integrated driver and spaced apart from each other; and
an opening portion configured to expose an upper surface of the substrate and obtained by removing a plurality of inorganic insulating layers disposed in the area between the plurality of test lines.

2. The display apparatus according to claim 1 , wherein the plurality of test lines are disposed between an end of the substrate and the integrated driver.

3. The display apparatus according to claim 1 , wherein the opening portion is disposed between an end of the substrate and the integrated driver.

4. The display apparatus according to claim 1 , further comprising an organic film disposed to cover an edge of the opening portion.

5. The display apparatus according to claim 4 , wherein the organic film covers a boundary surface between the substrate and a lowermost inorganic insulating layer among the plurality of inorganic insulating layers in the edge of the opening portion.

6. The display apparatus according to claim 5 , wherein the organic film covers lateral surfaces of the plurality of inorganic insulating layers in the edge of the opening portion.

7. The display apparatus according to claim 6 , wherein the plurality of inorganic insulating layers include a buffer insulating layer, a gate insulating layer, a first interlayer insulating layer, a second interlayer insulating layer and a protection insulating layer.

8. The display apparatus according to claim 7 ,
wherein the thin film transistor includes a semiconductor layer disposed on the buffer insulating layer, a gate electrode overlapped with the semiconductor layer under a condition that the gate insulating layer is interposed in-between, the first and second interlayer insulating layers disposed on the gate electrode, and source and drain electrodes disposed on the second interlayer insulating layer and connected with the semiconductor layer, and
the protection insulating layer is disposed on the thin film transistor.

9. The display apparatus according to claim 7 , wherein the organic film covers the boundary surface between the substrate and the buffer insulating layer in the edge of the opening portion.

10. The display apparatus according to claim 7 , wherein the organic film extends to cover lateral surfaces of the buffer insulating layer, the gate insulating layer, the first interlayer insulating layer, the second interlayer insulating layer and the protection insulating layer in the edge of the opening portion.

11. The display apparatus according to claim 3 , wherein the end of the substrate corresponds to a trimming line.

12. The display apparatus according to claim 11 , wherein the opening portion is overlapped with the trimming line.

13. An electroluminescence display comprising a substrate having a display area and a non-display area, a thin film transistor disposed on the display area, and a light emitting diode connected with the thin film transistor under a condition that a protection insulating layer and a first planarization layer are interposed in-between,
wherein the non-display area includes:
an integrated driver electrically connected with the thin film transistor of the display area;
a plurality of test lines connected with the integrated driver and extending to the outermost line of the substrate; and
an opening portion overlapped with an outermost line of the substrate, and

configured to expose an upper surface of the substrate by removing a plurality of inorganic insulating layers disposed in the area between the plurality of test lines spaced apart from each other.

14. The electroluminescence display according to claim 13 , wherein the outermost line of the substrate corresponds to a trimming line.

15. The electroluminescence display according to claim 14 , further comprising an organic film disposed to cover an edge of the opening portion.

16. The electroluminescence display according to claim 15 , wherein the organic film covers a boundary surface between the substrate and a lowermost insulating layer among the plurality of inorganic insulating layers in the edge of the opening portion, and the organic film extends to cover lateral surfaces of the plurality of inorganic insulating layers.

17. The electroluminescence display according to claim 16 , wherein the plurality of inorganic insulating layers include a buffer insulating layer, a gate insulating layer, a first interlayer insulating layer, a second interlayer insulating layer and a protection insulating layer.

18. The electroluminescence display according to claim 17 ,
wherein the thin film transistor includes a semiconductor layer disposed on the buffer insulating layer, a gate electrode overlapped with the semiconductor layer under the condition that the gate insulating layer is interposed in-between, the first and second interlayer insulating layers disposed on the gate electrode, and source and drain electrodes disposed on the second interlayer insulating layer and connected with the semiconductor layer, and
the protection insulating layer is disposed on the thin film transistor.

19. The electroluminescence display according to claim 18 , wherein the test line is disposed in the same layer as the source and drain electrodes of the thin film transistor, and is formed of the same material as that of the source and drain electrodes of the thin film transistor.

20. The electroluminescence display according to claim 16 , further comprising a second planarization layer disposed on the first planarization layer,
wherein the organic film is formed of at least one of the first planarization layer and the second planarization layer.

Assignees

• Lg Display Co Ltd

Inventors

• Yeo Junho

Classifications

• H10P74/273 Primary

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G3/32

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• H01L27/3258

  Electricity · mapped topic

• H01L27/3223 Primary

  Electricity · mapped topic