Decoupling capacitor

Patent metadata

Field	Value
Publication number	US-10497653-B2
Application number	US-201715788611-A
Country	US
Kind code	B2
Filing date	Oct 19, 2017
Priority date	Feb 13, 2017
Publication date	Dec 3, 2019
Grant date	Dec 3, 2019

Abstract

A decoupling capacitor includes: two capacitor cells sharing the same well; a first trench isolation passing through the well between the two cells without reaching the bottom of the well; and a contact with the well formed in each cell.

First claim

The invention claimed is:

1. A decoupling capacitor comprising:
first and second capacitor cells sharing a well with each other;
a first trench isolation passing through the well between the two cells without reaching a bottom of the well; and
first and second conductive contacts respectively connected to the first and second capacitor cells.

2. The decoupling capacitor according to claim 1 , further comprising conductive first and second lateral supply strips and a conductive central supply strip, wherein the first capacitor cell is positioned between the first lateral supply strip and the central supply strip and the second capacitor cell is positioned between the second lateral supply strip and the central supply strip.

3. The decoupling capacitor according to claim 2 , wherein the first trench isolation includes a conductive core and a dielectric cladding that surrounds the conductive core and insulates the conductive core from the well, the central supply strip being electrically coupled to the conductive core.

4. The decoupling capacitor according to claim 1 , further comprising second trench isolations extending longitudinally in the well in a direction orthogonal to a longitudinal extension of the first trench isolation.

5. The decoupling capacitor according to claim 1 , further comprising:
a substrate in which the well is formed;
a third capacitor cell including a second trench isolation formed in the substrate and outside of the well; and
a fourth capacitor cell including a third trench isolation formed in the substrate and outside of the well.

6. The decoupling capacitor according to claim 5 , wherein the second trench isolation encircles three sides of a first half of the well and the third trench isolation encircles three sides of a second half of the well.

7. The decoupling capacitor according to claim 5 , wherein each of the second and third trench isolations includes a conductive core and a dielectric cladding that surrounds the conductive core and insulates the conductive core from the substrate.

8. The decoupling capacitor according to claim 5 , further comprising a shallow trench insulation that completely encircles the well and separates the second and third trench isolations from the well.

9. An integrated circuit comprising:
a decoupling capacitor that includes:
first and second capacitor cells sharing a well with each other;
a first trench isolation passing through the well between the two cells without reaching a bottom of the well; and
first and second conductive contacts respectively connected to the first and second capacitor cells; and

a detection circuit configured to detect an impedance between the first and second contacts.

10. The integrated circuit according to claim 9 , wherein the decoupling capacitor includes conductive first and second lateral supply strips and a conductive central supply strip, wherein the first capacitor cell is positioned between the first lateral supply strip and the central supply strip and the second capacitor cell is positioned between the second lateral supply strip and the central supply strip.

11. The integrated circuit according to claim 10 , wherein the first trench isolation includes a conductive core and a dielectric cladding that surrounds the conductive core and insulates the conductive core from the well, the central supply strip being electrically coupled to the conductive core.

12. The integrated circuit according to claim 9 , wherein the decoupling capacitor includes second trench isolations extending longitudinally in the well in a direction orthogonal to a longitudinal extension of the first trench isolation.

13. The integrated circuit according to claim 9 , wherein the decoupling capacitor includes:
a substrate in which the well is formed;
a third capacitor cell including a second trench isolation formed in the substrate and outside of the well; and
a fourth capacitor cell including a third trench isolation formed in the substrate and outside of the well.

14. The integrated circuit according to claim 13 , wherein the second trench isolation encircles three sides of a first half of the well and the third trench isolation encircles three sides of a second half of the well.

15. The integrated circuit according to claim 13 , wherein each of the second and third trench isolations includes a conductive core and a dielectric cladding that surrounds the conductive core and insulates the conductive core from the substrate.

16. The integrated circuit according to claim 13 , further comprising a shallow trench insulation that completely encircles the well and separates the second and third trench isolations from the well.

17. A method of using a decoupling capacitor that includes first and second capacitor cells sharing a well with each other; a first trench isolation passing through the well between the two cells without reaching a bottom of the well; and first and second conductive contacts respectively connected to the first and second capacitor cells, the method comprising:
setting the first and second conductive contacts to first and second voltages, respectively, the first and second voltages being different from each other; and
measuring an impedance across the well while the first and second conductive contacts are set at the first and second voltages, respectively.

18. The method according to claim 17 , wherein the decoupling capacitor includes conductive first and second lateral supply strips and a conductive central supply strip, wherein the first capacitor cell is positioned between the first lateral supply strip and the central supply strip and the second capacitor cell is positioned between the second lateral supply strip and the central supply strip, the method including providing a first supply voltage to the first and second lateral supply strips and a second supply voltage to the central supply strip.

19. The method according to claim 18 , wherein the first trench isolation includes a conductive core and a dielectric cladding that surrounds the conductive core and insulates the conductive core from the well, the central supply strip being electrically coupled to the conductive core, wherein applying the second supply voltage to the central supply strip also supplies the second supply voltage to the conductive core.

Assignees

• St Microelectronics Crolles 2 Sas
• St Microelectronics Rousset

Inventors

• Lisart Mathieu
• Froment Benoit

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10W42/405

  using active circuits · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/427

  Power or ground buses · CPC title