System level simulation in Network on Chip architecture

Patent metadata

Field	Value
Publication number	US-10496770-B2
Application number	US-201615265177-A
Country	US
Kind code	B2
Filing date	Sep 14, 2016
Priority date	Jul 25, 2013
Publication date	Dec 3, 2019
Grant date	Dec 3, 2019

Abstract

Systems and methods for performing multi-message transaction based performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect architecture by accurately imitating full SoC behavior are described. The example implementations involve simulations to evaluate and detect NoC behavior based on execution of multiple transactions at different rates/times/intervals, wherein each transaction can contain one or more messages, with each message being associated with a source agent and a destination agent. Each message can also be associated with multiple parameters such as rate, size, value, latency, among other like parameters that can be configured to indicate the execution of the transaction by a simulator to simulate a real-time scenario for generating performance reports for the NoC interconnect.

First claim

What is claimed is:

1. A non-transitory computer readable storage medium storing instructions for executing a process, the instructions comprising:
performing, on a computer, a simulation of a Network-on-Chip (NoC) interconnect by using a plurality of transactions, wherein each of the plurality of transactions comprises a sequence of one or more messages, and wherein each of the one or more messages comprises an indication for at least one of a source and a destination agent; and
generating subsequent messages in the sequence of the one or more messages for ones of the plurality of transactions based on a first message destination node in the sequence of the one or more messages, wherein the subsequent messages are generated at each destination node of the one or more messages.

2. The non-transitory computer readable storage medium of claim 1 , wherein each of the one or more messages comprises an indication for at least one of a rate, a priority, a value, a message data size, latency, and an interval, and wherein messages are used for performing the simulation based on at least one of the rate, the priority, the value, the message data size, the latency and the interval.

3. The non-transitory computer readable storage medium of claim 2 , wherein each of the one or more messages comprises an indication for a rate, wherein the rate comprises an indication of a probability of selection of a respective message during the simulation.

4. The non-transitory computer readable storage medium of claim 1 , the instructions further comprising generating a trace file for each agent based on the ones of the plurality of transaction sequences that originate from the each agent, wherein the trace file comprises a subset of the one or more messages in the ones of the plurality of transaction sequences.

5. The non-transitory computer readable storage medium of claim 1 , the instructions further comprising generating a performance report of the NoC interconnect based on the simulation.

6. A non-transitory computer readable storage medium storing instructions for executing a process, the instructions comprising:
performing a simulation of a Network-on-Chip (NoC) interconnect by using a plurality of transactions, wherein each of the plurality of transactions comprises a sequence of one or more messages, and wherein each of the one or more messages comprises an indication for at least one of a source and a destination agent,
wherein each of the one or more messages comprises an indication for a rate and at least one of a priority, a value, a message data size, latency, and an interval, and wherein the one or more messages are used for performing the simulation based on at least one of the rate, the priority, the value, the message data size, the latency and the interval, and
wherein the rate comprises an indication of a probability of selection of a respective message during the simulation.

7. The non-transitory computer readable storage medium of claim 6 , wherein the instructions further comprise generating a trace file for each agent based on the ones of the plurality of transaction sequences that originate from the each agent, wherein the trace file comprises an indication of the one or more messages for each of the plurality of transaction sequences.

8. The non-transitory computer readable storage medium of claim 6 , wherein the instructions further comprise generating subsequent messages for ones of the plurality of transaction sequences based on a first message destination node.

9. The non-transitory computer readable storage medium of claim 6 , wherein the instructions further comprise generating a performance report of the NoC interconnect based on the simulation.

10. A method, comprising:
performing a simulation of a Network-on-Chip (NoC) interconnect by using a plurality of transactions, wherein each of the plurality of transactions comprises a sequence of one or more messages, and wherein each of the one or more messages comprises an indication for at least one of a source and a destination agent,
wherein each of the one or more messages comprises an indication for a rate and at least one of a priority, a value, a message data size, latency, and an interval, and wherein the one or more messages are used for performing the simulation based on at least one of the rate, the priority, the value, the message data size, the latency and the interval, and
wherein the rate comprises an indication of a probability of selection of a respective message during the simulation.

11. The method of claim 10 , further comprising generating a trace file for each agent based on the ones of the plurality of transaction sequences that originate from the each agent, wherein the trace file comprises an indication of the one or more messages for each of the plurality of transaction sequences.

12. The method of claim 10 , further comprising generating subsequent messages for ones of the plurality of transaction sequences based on a first message destination node.

13. The method of claim 10 , further comprising generating a performance report of the NoC interconnect based on the simulation.

14. A method comprising:
performing, on a computer, a simulation of a Network-on-Chip (NoC) interconnect by using a plurality of transactions, wherein each of the plurality of transactions comprises a sequence of one or more messages, and wherein each of the one or more messages comprises an indication for at least one of a source and a destination agent; and
generating subsequent messages in the sequence of the one or more messages for ones of the plurality of transactions based on a first message destination node in the sequence of the one or more messages, wherein the subsequent messages are generated at each destination node of the one or more messages.

15. The method of claim 14 , wherein each of the one or more messages comprises an indication for at least one of a rate, a priority, a value, a message data size, latency, and an interval, and wherein messages are used for performing the simulation based on at least one of the rate, the priority, the value, the message data size, the latency and the interval.

16. The method of claim 14 , wherein each of the one or more messages comprises an indication for a rate, wherein the rate comprises an indication of a probability of selection of a respective message during the simulation.

17. The method of claim 14 , further comprising generating a trace file for each agent based on the ones of the plurality of transaction sequences that originate from the each agent, wherein the trace file comprises a subset of the one or more messages in the ones of the plurality of transaction sequences.

18. The method of claim 14 , further comprising generating a performance report of the NoC interconnect based on the simulation.

Assignees

• Netspeed Systems

Inventors

• Kumar Sailesh
• Patankar Amit
• Norige Eric

Classifications

• G06F30/33 Primary

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F15/7807

  System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package · CPC title

• G06F17/5022 Primary

  Physics · mapped topic

• G06F17/5009

  Physics · mapped topic