System on chip and method of executing a process in a system on chip

Patent metadata

Field	Value
Publication number	US-10496554-B2
Application number	US-201414194862-A
Country	US
Kind code	B2
Filing date	Mar 3, 2014
Priority date	Mar 3, 2014
Publication date	Dec 3, 2019
Grant date	Dec 3, 2019

Abstract

A system on chip, comprising a processing unit for executing processes, a memory unit, and a memory control unit connected between the processing unit and the memory unit, is described. The memory control unit allocates a memory region to a process. The memory control unit comprises a process activity counter which counts a duration of the process or transactions by the process to or from the memory region and which maintains a process activity count representing the counted duration of the process or the counted transactions to or from the memory region. The memory control unit disables the memory region in response to the process activity count exceeding a maximum process activity count. Notably, it blocks the memory region against further transactions by the process and against transactions by any other processes.
A method of operating a system on chip is also described.

First claim

The invention claimed is:

1. A system on chip, comprising:
a processing unit to execute processes;
a memory unit; and
a memory control unit connected between the processing unit and the memory unit the memory control unit to allocate a memory region to a process, the memory control unit includes:
a process activity counter to count a duration of the process, and to maintain a process activity count representing the counted duration of the process, wherein the count of the duration of the process starts with an execution of a first instruction by the process, wherein the duration of the process is a length of time that the process has been executing instructions;

wherein the memory control unit is arranged to disable the memory region in response to the process activity count exceeding a maximum process activity count, wherein the maximum process activity count is a predefined time that the process has been executing instructions, wherein disabling the memory region includes blocking the memory region against further transactions by the process and against transactions by any other processes.

2. The system on chip of claim 1 , wherein the process activity counter is arranged to count each clock cycle of the process.

3. The system on chip of claim 1 , wherein said memory region is a data memory region.

4. The system on chip of claim 1 , wherein the maximum process activity count is user configurable.

5. The system on chip of claim 1 , wherein the maximum process activity count is stored at a memory location that is not accessible by the processing unit or that is write-protected against the processing unit.

6. The system on chip of claim 1 , wherein the control unit is arranged to disable the memory region in response to the process activity count failing to reach a minimum process activity count.

7. The system on chip of claim 1 , wherein the processing unit comprises one or more processor cores.

8. The system on chip of claim 1 , wherein the processing unit is capable of running multiple processes simultaneously or quasi-simultaneously;
wherein the memory control unit is arranged to allocate a memory region to each process among multiple processes which are being executed or which are scheduled to be executed simultaneously or quasi-simultaneously;
wherein the memory control unit comprises a set of process activity counters, wherein each process activity counter is associated with one of the multiple processes and arranged to count a duration of the respective process or to count transactions by the process to or from the memory region allocated to the respective process, and to maintain a process activity count representing the counted duration of the process or the counted transactions to or from the memory region; and
wherein the memory control unit is arranged to disable, for each of the memory regions allocated to the multiple processes, the respective memory region in response to the respective process activity count exceeding a respective maximum process activity count, wherein disabling the memory region includes blocking the respective memory region against further transactions by the respective process and against transactions by any other processes.

9. The system on chip of claim 1 , configured to provide one or more programs, wherein a maximum process activity count is provided individually for each program among two or more programs on the system on chip wherein all instances of any one of the programs have the same maximum process activity count.

10. The system on chip of claim 1 , wherein the memory control unit is arranged to disable the memory region along with one or more other memory regions in response to the process activity count exceeding the maximum process activity count.

11. The system on chip of claim 10 , wherein said one or more other memory regions are memory regions not allocated to the process.

12. The system on chip of claim 1 , wherein transactions are allowed to other memory regions while the memory region is disabled in response to the memory control unit not restricting access to the other memory regions in response to the process activity count exceeding the maximum process activity count.

13. The method of claim 12 , wherein the control unit is arranged to disable the memory region in response to the process activity count failing to reach a minimum process activity count.

14. The method of claim 12 , wherein the maximum process activity count is stored at a memory location that is not accessible by the processing unit or that is write-protected against the processing unit.

15. The method of claim 12 , wherein the memory control unit is arranged to disable the first memory region along with one or more other memory regions in response to the first process activity count exceeding the first maximum process activity count.

16. A method of executing a process in a system on chip, comprising:
allocating a memory region to the process;
starting the process and, while the process is running, counting a duration of the process, and maintaining a process activity count which represents the counted duration of the process, wherein the count of the duration of the process starts with an execution of a first instruction by the process, wherein the duration of the process is a length of time that the process has been executing instructions;
disabling the memory region in response to the process activity count exceeding a maximum process activity count, wherein the maximum process activity count is a predefined time that the process has been executing instructions, wherein disabling the memory region includes blocking the memory region against further transactions by the process and against transactions by any other processes.

17. The method of claim 16 , wherein the maximum process activity count is stored at a memory location that is not accessible by the processing unit or that is write-protected against the processing unit.

18. The method of claim 16 , wherein the control unit is arranged to disable the memory region in response to the process activity count failing to reach a minimum process activity count.

19. A method of executing processes in a system on chip, comprising:
allocating a first memory region to a first process and a second memory region to a second process;
starting the first and second processes;
while the first process is running, counting a first duration of the first process, wherein a first count of the first duration of the first process starts with an execution of a first instruction by the first process, wherein the duration of the first process is a length of time that the first process has been executing instructions;
maintaining a first process activity count which represents the first count of the first duration of the first process;
disabling the first memory region for accesses in response to the first process activity count exceeding a first maximum process activity count, wherein the first maximum process activity count is a first predefined time that the first process has been executing instructions, wherein disabling the first memory region for accesses includes blocking access to the first memory region by the first process and by any other processes;
while the second process is running, counting a second duration of the second process, wherein a second count of the second duration of the second process starts with an execution a first instruction by the second process, wherein the duration of the second process is a length of time that the second process has been

Assignees

• Johnston Michael
• Devine Alan
• Robertson Alistair Paul
• Thanner Manfred
• Nxp Usa Inc

Inventors

• Johnston Michael
• Devine Alan
• Robertson Alistair Paul
• Thanner Manfred

Classifications

• G06F12/1475 Primary

  in a virtual system, e.g. with translation means · CPC title

• G06F21/71

  to assure secure computing or processing of information · CPC title

• G06F21/52

  during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} · CPC title

• G06F2212/1052

  Security improvement · CPC title

• G06F12/0284 Primary

  Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163) · CPC title